Agilent Technologies 75000 SERIES B, E1301B Output 70900*PSC, Output 70900*SRE, Output 70900*ESE

NOTE	The System Instrument no longer implements the *LRN? command.
	Attempting to have the System Instrument execute this command will generate
	an error -113 “Undefined header”.

*OPC Operation Complete. Causes an instrument to set bit 0 (Operation Complete Message) in the Standard Event Status Register when all pending operations have been completed. By enabling this bit to be reflected in the Status Byte Register (*ESE 1 command), you can ensure synchronization between the instrument and an external computer or between multiple instruments. (Refer to "Synchronizing an External Computer and Instruments" earlier in this chapter for an example).

*OPC? Operation Complete Query. Causes an instrument to place an ASCII 1 into the instrument’s output queue when all pending instrument operations are finished. By requiring the computer to read this response before continuing program execution, you can ensure synchronization between one or more instruments and the computer. (Refer to "Synchronizing an External Computer and Instruments" earlier in this chapter for an example).

*PMC Purge Macros Command. Purges all currently defined macros in the selected instrument.

*PSC < flag> Power-on Status Clear Command. Controls the automatic power-on clearing of the Service Request Enable register and Standard Event Status Enable register. Executing *PSC 1 disables any previously enabled bits at power-on, preventing the System Instrument from requesting service when power is cycled. Executing *PSC 0 causes any previously enabled bits to remain enabled at power-on which allows the System Instrument to request service (if it has been enabled - *SRE) when power is cycled. The value of flag is stored in non-volatile memory.

Example This example configures the System Instrument to request service from the external computer whenever power is cycled.

Status Byte register and Standard Event Status register bits remain enabled (unmasked) after cycling power

10 OUTPUT 70900;"*PSC 0"

Enable bit 5 (Standard Event Status Register Summary Bit) in the Status Byte Register

20 OUTPUT 70900;"*SRE 32"

Enable bit 7 (Power-on bit) in the Standard Event Status

Register to be reflected as bit 5 in the Status Byte Register

30 OUTPUT 70900;"*ESE 128"

*PSC? Power-on status clear query. Returns a response indicating whether an instrument’s Status Byte Register and Standard Event Status Register bits remain enabled or become disabled at power-on. A "1" means the bits are disabled at power-on; a "0" means the bits remain enabled at power-on.

System Instrument Command Reference 7-69