APPENDICES
APPENDIX 4 Differences Between Q173DCPU/Q172DCPU and Q173HCPU/Q172HCPU APPENDIX 4.1 Differences Between Q173DCPU/Q172DCPU and Q173HCPU/Q172HCPU
Common differences to each mode are shown in Table 4.1.
Refer to "APPENDIX 4.3 Differences of each mode" for characteristic differences to each mode.
And, refer to "APPENDIX 4.2 Comparison of devices " for detailed differences of devices.
Table 4.1 Differences Between Q173DCPU/Q172DCPU and Q173HCPU/Q172HCPU
| Item | Q173DCPU/Q172DCPU | Q173HCPU/Q172HCPU | |
Peripheral I/F | Via PLC CPU | USB/SSCNET | ||
External battery | Demand | Add Q6BAT at continuous power failure for 1 | ||
month or more. | ||||
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| • Use EMI terminal of Motion CPU module. | • Use device set by forced stop input setting in | |
Forced stop input | • Use device set by forced stop input setting in | |||
the system setting. | ||||
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| the system setting. | ||
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Multiple CPU high speed |
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transmission memory for data | Included | — | ||
transfer between CPU modules |
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| Internal relays (M) | 8192 points | Total 8192 points | |
| Latch relays (L) | None (Latch for M is possible by latch setting) | ||
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| Special relays (M) | — | 256 points | |
Device | Special relays (SM) | 2256 points | — | |
Special registers (D) | — | 256 points | ||
Special registers (SD) | 2256 points | — | ||
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| Motion registers (#) | 8736 points | 8192 points | |
| Multiple CPU area devices | Up to 14336 points | — | |
| (U \G) | |||
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| D(P).DDRD, D(P).DDWR, D(P).SFCS, | S(P).DDRD, S(P).DDWR, S(P).SFCS, | |
Motion dedicated PLC instructions | D(P).SVST, D(P).CHGT, D(P).CHGV, | S(P).SVST, S(P).CHGT, S(P).CHGV, | ||
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| D(P).CHGA, D(P).GINT | S(P).CHGA, S(P).GINT | |
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| Multiple instructions are executable continuously |
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| Interlock condition | without interlock condition by the self CPU high | Interlock condition by the to self CPU high speed | |
| speed interrupt accept flag from CPU . | interrupt accept flag from CPU is necessary. | ||
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| :CPU No. |
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Motion modules | Q172DLX, Q172DEX, Q173DPX | Q172LX, Q172EX, Q173PX | ||
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| • QnUD(H)CPU is set as CPU No. 1. |
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| • Only Multiple CPU high speed main base unit | • QnUD(H)CPU is set to CPU No. 1. | |
System setting | (Q38DB/Q312DB) can be used as main base | • Q3 B can be used as a main base unit. | ||
unit. | • Motion modules can be mounted to I/O 0 to 2 | |||
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| • Motion modules cannot be installed to I/O 0 to 2 | slot. | |
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| slot. |
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Latch clear | Remote operation | L.CLR switch | ||
RUN/STOP | Remote operation, RUN/STOP switch | RUN/STOP switch | ||
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| • ROM writing is executed with mode operated |
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ROM operation | by RAM/ mode operated by ROM. | Rom writing is executed with installation mode/ | ||
• ROM writing can be executed for the data of | mode written in ROM. | |||
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| MT Developer. |
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APP - 26