APPENDICES
Table 4.8 Other devices list (Continued)Limit switch output data
Item |
| Q173DCPU/Q172DCPU | Q173HCPU/Q172HCPU |
|
| X0 to X1FFF | X0 to X1FFF |
|
| Y0 to Y1FFF | Y0 to Y1FFF |
Output device |
| M0 to M8191 | M0 to M8191 |
| — | L0 to L8191 | |
|
| ||
|
| B0 to B1FFF | B0 to B1FFF |
| U | \G10000.0 to U \G(10000 + p | — |
|
| D0 to D8191 | D0 to D8191 |
|
| W0 to W1FFF | W0 to W1FFF |
Watch data |
| #0 to #7999 | #0 to #8191 |
|
| Absolute value address | Absolute value address |
| U | \G10000 to U \G(10000 + p | — |
|
| D0 to D8191 | D0 to D8191 |
|
| W0 to W1FFF | W0 to W1FFF |
ON region setting |
| #0 to #7999 | #0 to #8191 |
|
| Constant (Hn/Kn) | Constant (Hn/Kn) |
| U | \G10000 to U \G(10000 + p – 1) | — |
|
| X0 to X1FFF | X0 to X1FFF |
|
| Y0 to Y1FFF | Y0 to Y1FFF |
Output enable/disable bit |
| M0 to M8191 | M0 to M8191 |
| — | L0 to L8191 | |
|
| ||
Forced output bit |
| B0 to B1FFF | B0 to B1FFF |
| F0 to F2047 | F0 to F2047 | |
|
| ||
|
| SM0 to SM1999 | M9000 to M9255 |
| U \G10000.0 to U \G(10000 + p – 1).F | — |
POINT
Refer to Chapter 2 for number of user setting area points of Multiple CPU high speed transmission area.
APP - 34