2MULTIPLE CPU SYSTEM

(3)Memory configuration of Multiple CPU high speed transmission area

Memory configuration of Multiple CPU high speed transmission area is shown below.

 

1)

 

2)

CPU No.1 send area

6)

User setting area

 

 

 

Multiple CPU high speed

 

 

 

 

 

 

 

transmission area

 

 

 

 

 

 

 

 

 

 

 

[Variable in 0 to

 

3)

CPU No.2 send area

 

 

7) Automatic refresh area

 

 

 

14k[points] (Note-1)]

 

 

 

 

 

 

 

 

 

 

 

 

 

4)

CPU No.3 send area

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5)

CPU No.4 send area

 

 

 

 

 

 

 

 

 

(Note-1): Multiple CPU high speed transmission area;

 

 

 

 

 

 

 

 

14k[points]: Maximum value when constituted with two CPUs

 

 

 

 

 

 

 

13k[points]: Maximum value when constituted with three CPUs

 

 

 

 

 

 

 

12k[points]: Maximum value when constituted with four CPUs

 

 

 

 

Table 2.5Description of area

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

No.

 

 

Name

 

Description

 

 

Size

 

 

 

Setting range

Setting unit

 

 

 

 

 

 

 

 

 

 

 

 

 

• Area for data transmission between each CPU module

 

 

 

 

1)

Multiple CPU high speed

in the Multiple CPU system.

 

 

0 to 14k

1k

transmission area

• The area up to 14k [points] is divided between each

 

 

 

 

 

 

 

 

 

CPU module that constitutes the Multiple CPU system.

 

 

 

 

2)

 

 

 

• Area to store the send data of the each CPU module.

 

 

 

 

3)

 

CPU No. n send area

• Sends the data stored in the send area of self CPU to

 

 

 

 

4)

 

the other CPUs.

 

 

 

 

0 to 14k

1k

 

(n=1 to 4)

 

 

 

 

5)

 

• Other CPU send area stores the data received from

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the other CPUs.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• Area for data communication with other CPUs using

 

 

 

 

 

 

 

 

the Multiple CPU area device.

 

 

 

 

6)

 

 

User setting area

• Can be accessed by the user program using the

0 to 14k

2

 

 

 

 

Multiple CPU area device.

 

 

 

 

 

 

 

 

 

 

• Refer to Section 2.3.2 (1) for details of this area.

 

 

 

 

 

 

 

 

• Area for communicating device data with other CPUs

 

 

 

 

 

 

 

Automatic refresh

by the communication using the automatic refresh.

 

 

 

 

7)

 

 

• Access by user program is disabled.

0 to 14k

2

 

 

area

 

 

 

• Refer to Section "(4)(b) Automatic refresh setting" for

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

details of this area.

 

 

 

 

 

 

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