2 MULTIPLE CPU SYSTEM

2.3 Communication between the PLC CPU and the Motion CPU in the Multiple CPU System

2.3.1CPU shared Memory(1)Structure of CPU shared memory

The CPU shared memory is memory provided for each CPU module by which data is written or read between CPU modules of a Multiple CPU system.

The CPU shared memory consists of four areas.

•Self CPU operation information area

•System area

•User setting area

•Multiple CPU high speed transmission area

The CPU shared memory configuration and the availability of the communication from the self CPU using the CPU shared memory by program are shown below.

(0H)

0

to

to

(1FFH)

511

(200H)

512

to

to

(7FFH)

2047

(800H)

2048

to

to

(FFFH) 4095

(1000H) 4096

to to (270FH) 9999

(2710H) 10000

to to

up to (5F0FH) 24335

CPU shared memory

Self CPU operation

information area

System area

User setting area

Unusable

Multiple CPU high speed transmission area (Variable size in 0 to 14k[points]: 1k words in unit)

 

Self CPU

Other CPU

 

Write

Read

Write

Read

 

 

(Note-2)

 

(Note-2)

 

 

 

 

 

 

 

 

 

(Note-2)

 

 

 

 

 

 

(Note-1)

(Note-2)

 

(Note-2)

Multiple CPU

(Note-3)

(Note-3)

(Note-3)

high speed

 

 

 

bus

 

 

 

: Communication allowed : Communication not allowed

REMARK

(Note-1) : Use the MULTW instruction to write to the user setting area of the self CPU in the Motion CPU.

Use the S. TO instruction to write to the user setting area of the self CPU in the PLC CPU.

(Note-2) : Use the MULTR instruction to read the shared memory of self CPU and other CPU in the Motion CPU.

Use the FROM instruction/Multiple CPU area device (U\G) to read the shared memory of the Motion CPU from the PLC CPU.

(Note-3) : Refer to Section 2.3.2(1) for the access method of Multiple CPU high speed transmission area.

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