2MULTIPLE CPU SYSTEM
(a)Self CPU operation information area (0H to 1FFH)
1)The following information of self CPU is stored as the Multiple CPU system
Table 2.3 Table of self CPU operation information areasCPU shared |
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| Description (Note) | Corresponding | |
memory | Name | Detail |
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address |
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| special register | |
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| The area to confirm if information is stored in the self CPU's |
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| Information availability | operation information area (1H to 1FH) or not. |
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0H | Information availability | • | 0: Information not stored in the self CPU's operation information | — | ||
flag |
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| • | 1: Information stored in the self CPU's operation information |
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| area. |
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1H | Diagnostic error | Diagnostic error number | An error No. identified during diagnosis is stored in BIN. | SD0 | ||
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| The year and month that the error number was stored in the CPU |
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2H |
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| shared memory's 1H address is stored with two digits of the BCD | SD1 | ||
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| code. |
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| Time the diagnostic error | Time the diagnostic error | The date and time that the error number was stored in the CPU |
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3H | shared memory's 1H address is stored with two digits of the BCD | SD2 | ||||
occurred | occurred | |||||
| code. |
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| The minutes and seconds that the error number was stored in the |
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4H |
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| CPU shared memory's 1H address is stored with two digits of the | SD3 | ||
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| BCD code. |
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| Error information | Error information | Stores an identification code to determine what error information |
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5H | has been stored in the common error information and individual | SD4 | ||||
identification code | identification code | |||||
| error information. |
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6H to 10H | Common error information | Common error information | The common information corresponding to the error number | SD5 to SD15 | ||
identified during diagnosis is stored. | ||||||
11H to 1BH | Individual error | Individual error | The individual information corresponding to the error number | SD16 to SD26 | ||
information | information | identified during diagnostic is stored. | ||||
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1CH | Empty | — | Cannot be used | — | ||
1DH | Switch status | CPU switch status | Stores the CPU module switch status. | SD200 | ||
1EH | Empty | — | Cannot be used | — | ||
1FH | CPU operation status | CPU operation status | Stores the CPU module's operation status. | SD203 | ||
(Note) : Refer to the corresponding special register for details.
2)The self CPU operation information area is refreshed every time the applicable register has been changed in the main cycle.
3)Other PLC CPU can use FROM instruction to read data from the self CPU operation information area.
However, because there is a delay in data updating, use the read data for monitoring purposes only.
(b)System area
The area used by the operating systems (OS) of the PLC CPU/Motion CPU.
(c)User setting area
The area for communication between CPU modules in the Multiple CPU system by MULTR/MULTW instruction of Motion CPU.
(PLC CPU use FROM/S.TO instruction or Multiple CPU area devices to communicate between CPU modules.)
Refer to the Programming Manual of operating system software for MULTR/MULTW instruction.
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