2MULTIPLE CPU SYSTEM

(d)Multiple CPU high speed transmission area

The area corresponding to the Multiple CPU high speed main base unit (Q3DB) and Multiple CPU high speed transmission that uses the drive system controllers including QnUD(H)CPU and Motion CPU.

The image chart of Multiple CPU high speed transmission area is shown below.

Refer to Section 2.3.2(1) for access to the Multiple CPU high speed transmission area of self CPU and other CPU.

 

 

CPU No.1

 

U3E0\G10000

CPU No.1 (Note-2)

 

Multiple CPU high

 

 

 

 

 

 

speed transmission

 

to

 

area

 

U3E0\G

(Note-1)

(Transmission)

 

 

 

 

U3E1\G10000

CPU No.2

 

Multiple CPU high

 

 

 

 

 

 

speed transmission

 

to

 

area

 

U3E1\G

(Note-1)

(Reception)

 

 

 

 

U3E2\G10000

CPU No.3

 

Multiple CPU high

 

 

 

 

 

 

speed transmission

 

to

 

area

 

 

 

(Reception)

 

U3E2\G

(Note-1)

 

 

U3E3\G10000

CPU No.4

 

Multiple CPU high

 

 

 

 

 

 

speed transmission

 

to

 

area

 

 

 

(Reception)

 

U3E3\G

(Note-1)

 

 

CPU No.2

 

CPU No.3

 

CPU No.4

CPU No.1

 

CPU No.1

 

CPU No.1

Multiple CPU high

 

Multiple CPU high

 

Multiple CPU high

speed transmission

 

speed transmission

 

speed transmission

area

 

area

 

area

(Reception)

 

(Reception)

 

(Reception)

CPU No.2 (Note-2)

 

 

 

 

 

CPU No.2

 

CPU No.2

Multiple CPU high

 

Multiple CPU high

 

Multiple CPU high

speed transmission

 

speed transmission

 

speed transmission

area

 

area

 

area

(Transmission)

 

(Reception)

 

(Reception)

 

 

 

 

 

 

 

 

 

 

CPU No.3

 

CPU No.3 (Note-2)

 

CPU No.3

Multiple CPU high

 

Multiple CPU high

 

Multiple CPU high

speed transmission

 

speed transmission

 

speed transmission

area

 

area

 

area

(Reception)

 

(Transmission)

 

(Reception)

 

 

 

 

 

 

 

 

 

 

 

 

CPU No.4

 

CPU No.4

 

CPU No.4 (Note-2)

Multiple CPU high

 

Multiple CPU high

 

Multiple CPU high

speed transmission

 

speed transmission

 

speed transmission

area

 

area

 

area

(Reception)

 

(Reception)

 

(Transmission)

 

 

 

 

 

 

 

(Note-1) : The final device is "10000+(A1024-B-1)".

A : Data transmission size of each CPU (1k words in unit)

B : Size used in the automatic refresh of each CPU.

Refer to Section "2.3.2 Multiple CPU high speed transmission" for the size setting of A and B.

(Note-2) : Transmission area to write/read in the self CPU. Reception area from the other CPU can be read only. It is updated every 0.88ms.

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