Clock Generator Module (CGM)
CGM Registers
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Clock Generator Module (CGM) 123
8.6 CGM Registers
These registers control and monitor operation of the CGM:
• PLL control register (PCTL)
See 8.6.1 PLL Control Register.
• PLL bandwidth control register (PBWC)
See 8.6.2 PLL Bandwidth Control Register.
• PLL programming register (PPG)
See 8.6.3 PLL Programming Register.
Figure 8-4 is a summary of the CGM registers.
Addr. Register Name Bit 7654321Bit 0
$005C PLL Control Register
(PCTL)
See page 124.
Read: PLLIE PLLF PLLON BCS 1111
Write: R R R R R
Reset:00101111
$005D PLL Bandwidth Control Register
(PBWC)
See page 126.
Read: AUTO LOCK ACQ XLD 0000
Write: R R R R R
Reset:00000000
$005E PLL Programming Register
(PPG)
See page 128.
Read: MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4
Write:
Reset:01100110
R= Reserved
Notes:
1. When AUTO = 0, PLLIE is forced to logic 0 and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic 0.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 8-4. CGM I/O Register Summary