Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Clock Generator Module (CGM) 131
Other systems refer to acquisition and lock times as the time the system
takes to reduce the error between the actual output and the desired
output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may
not even be registered. Typical PLL applications prefer to use this
definition because the system requires the output frequency to be within
a certain tolerance of the desired frequ ency regardless of the size of the
initial error.
The discrepancy in these definitions makes it difficult to specify an
acquisition or lock time for a typical PLL. Therefore, the definitions for
acquisition and lock times for this module are:
• Acquisition time, tACQ, is the time the PLL takes to reduce the error
between the actual output frequency and the desired output
frequency to less than the tracking mode entry tolerance, ∆TRK.
Acquisition time is based on an initial frequency error,
(fDES – fORIG)/fDES, of not more than ±100 percent. In automatic
bandwidth control mode (see 8.4.2.3 Manual and Automatic PLL
Bandwidth Modes), acquisition time expires when the ACQ bit
becomes set in the PLL bandwidth control register (PBWC).
• Lock time, tLock, is the time the PLL takes to reduce the error
between the actual output frequency and the desired output
frequency to less than the lock mode entry tol e ra nce , ∆Lock. Lock
time is based on an initial frequency error, (fDES – fORIG)/fDES, of
not more than ±100 percent. In automatic bandwidth control
mode, lock time expires when the LOCK bit becomes set in the
PLL bandwidth control register (PBWC). See 8.4.2.3 Manual and
Automatic PLL Bandwidth Modes.
Obviously, the acquisition and lock times can vary according to how
large the frequency error is and may be shorter or long er in many case s.