Pulse-Width Modulator for Motor Control (PWMMC)
Fault Protection
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Pulse-Width Modulator for Motor Control (PWMMC) 165
Figure 9-28. PWM Disabling in Manual Mode (Example 1)
Figure 9-29. PWM Disabling in Manual Mode (Example 2)
9.7.2 Software Output Disable
Setting PWM disable bit DISX or DISY in PWM control register 1
immediately disables the corresponding PWM pins as determined by the
bank and disable mapping register. The PWM pin(s) remain disabled
until the PWM disable bit is cleared and a new PWM cycle begins as
shown in Figure 9-30. Setting a PWM disable bit does not latch a CPU
interrupt request, and there are no event flags associated with the PWM
disable bits.
PWM(S) ENABLED PWM(S) ENABLED
PWM(S) DISABLED
FFLAGX CLEARED
FILTERED FAULT PIN 1 OR 3
PWM(S) ENABLED PWM(S) ENABLED
PWM(S) DISABLED
FFLAGX CLEARED
FILTERED FAULT PIN 2 OR 4