Pulse-Width Modulator for Motor Control (PWMMC)
Fault Protection
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Pulse-Width Modulator for Motor Control (PWMMC) 163
Figure 9-26. PWM Disabling Decode Scheme
9.7.1.2 Automatic Mode
In automatic mode, the PWM(s) are disabled immediately once a filtered
fault condition is detected (logic high). The PWM(s) remain d isabled until
the filtered fault condition is cleared (logic low) and a new PWM cycle
begins as shown in Figure 9-27. Clearing the corresponding FFLAGx
event bit will not enable the PWMs in automatic mode.
Figure 9-27. PWM Disabling in Automatic Mode
BIT 7
BIT 3
BIT 0
BIT 1
BIT 2
BIT 4
BIT 5
BIT 6
BANK X
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
BANK Y
PWM PIN 1
PWM PIN 2
PWM PIN 3
PWM PIN 4
PWM PIN 5
PWM PIN 6
PWM(S) ENABLED PWM(S) ENABLED
PWM(S) DISABLED (INACTIVE)
FILTERED FAULT PIN