Motorola MC68HC908MR16, MC68HC908MR32 - page 216

Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
216 Timer Interface A (TIMA) MOTOROLA
Timer Interface A (TIMA)
11.8.2 TIMA Counter Registers
The two read-only TIMA counter registers contain the high and lo w bytes
of the value in the TIMA counter. Reading the high byte (TACNTH)
latches the contents of the low byte (TACNTL) into a buff er. Subsequent
reads of TACNTH do not affect the latched TACNTL value until TACNTL
is read. Reset clears the TIMA counter registers. Setting the TIMA r eset
bit (TRST) also clears the TIMA counter registers.
NOTE: If TACNTH is read during a break interrupt, be sure to unlatch TACN TL
by reading TACNTL before exiting the break interrupt. Otherwise,
TACNTL retains the value latched during the break.
Table 11-1. Prescaler Selection
PS[2:0] TIMA Clock Source
000 Internal bus clock ÷1
001 Internal bus clock ÷ 2
010 Internal bus clock ÷ 4
011 Internal bus clock ÷ 8
100 Internal bus clock ÷ 16
101 Internal bus clock ÷ 32
110 Internal bus clock ÷ 64
111 PTE3/TCLKA
Register Name and Address: TACNTH — $000F
Bit 7654321Bit 0
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:RRRRRRRR
Reset:00000000
Register Name and Address: TACNTL — $0010
Bit 7654321Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:RRRRRRRR
Reset:00000000
R= Reserved
Figure 11-5. TIMA Counter Registers (TACNTH and TACNTL)