Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
128 Clock Generator Module (CGM) MOTOROLA
Clock Generator Module (CGM)
8.6.3 PLL Programming Register
The PLL programming register (PPG) contains the programming
information for the modulo feedback divider and the programming
information for the hardware configuration of the VCO.
MUL[7:4] — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. See 8.4.2.1 PLL Circuits and
8.4.2.4 Programming the PLL. A value of $0 in the multiplier select
bits configures the modulo feedback div ider the same as a value of
$1. Reset initializes these bits to $6 to give a default multiply value
of 6.
NOTE: The multiplier select bits have built-in protection th at prevents them fr om
being written when the PLL is on (PLLON = 1).
Address: $005E
Bit 7654321Bit 0
Read: MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4
Write:
Reset:01100110
Figure 8-7. PLL Programming Register (PPG)
Table 8-2. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4 VCO Frequency Multiplier (N)
0000 1
0001 1
0010 2
0011 3
1101 13
1110 14
1111 15