Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
24 List of Figures MOTOROLA
List of Figures
Figure Title Page
11-4 TIMA Status and Control Register (TASC). . . . . . . . . . . . .214
11-5 TIMA Counter Registers (TACNTH and TACNTL). . . . . . .216
11-6 TIMA Counter Modulo Registers
(TAMODH and TAMODL) . . . . . . . . . . . . . . . . . . . . . . .217
11-7 TIMA Channel Status and Control Registers
(TASC0–TASC3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
11-8 CHxMAX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
11-9 TIMA Channel Registers
(TACH0H/L–TACH3H/L). . . . . . . . . . . . . . . . . . . . . . . .222
12-1 TIMB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
12-2 TIMB I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .228
12-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . .232
12-4 TIMB Status and Control Register (TBSC). . . . . . . . . . . . .238
12-5 TIMB Counter Registers (TBCNTH and TBCNTL). . . . . . .240
12-6 TIMB Counter Modulo Registers
(TBMODH and TBMODL) . . . . . . . . . . . . . . . . . . . . . . .241
12-7 TIMB Channel Status and Control Registers
(TBSC0–TBSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
12-8 CHxMAX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
12-9 TIMB Channel Registers (TBCH0H/L–TBCH1H/L) . . . . . .246
13-1 SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .250
13-3 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . .251
13-2 SPI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .251
13-4 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . .254
13-5 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
13-6 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . .255
13-7 Transmission Start Delay (Master). . . . . . . . . . . . . . . . . . .257
13-8 Missed Read of Overflow Condition. . . . . . . . . . . . . . . . . .259
13-9 Clearing SPRF When OVRF Interrupt
Is Not Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
13-10 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . .263
13-11 SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . .265
13-12 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
13-13 SPI Control Register (SPCR). . . . . . . . . . . . . . . . . . . . . . .270
13-14 SPI Status and Control Register (SPSCR). . . . . . . . . . . . .272
13-15 SPI Data Register (SPDR). . . . . . . . . . . . . . . . . . . . . . . . .275