Motorola MC68HC908MR16, MC68HC908MR32 - page 126

Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
126 Clock Generator Module (CGM) MOTOROLA
Clock Generator Module (CGM)
8.6.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
• Selects automatic or manual (software-controlled) bandwidth
control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when t he PLL is in
acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking
mode
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control.
When initializing the PLL for manual operation (AUTO = 0), clear the
ACQ bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock, CGMVCLK, is locked (runni ng at the
programmed frequency). When the AUTO bit is clear, LOCK read s as
logic 0 and has no meaning. Reset clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
Address: $005D
Bit 7654321Bit 0
Read: AUTO LOCK ACQ XLD 0000
Write: R RRRR
Reset:00000000
R= Reserved
Figure 8-6. PLL Bandwidth Control Register (PBWC)