Pulse-Width Modulator for Motor Control (PWMMC)
Fault Protection
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Pulse-Width Modulator for Motor Control (PWMMC) 161
pin 1, fault pin 2, and PWM disable bit X constitute the disabling functio n
of bank X. Fault pin 3, fault pin 4, and PWM disable bit Y constitute the
disabling function of bank Y. Figure 9-24 and Figure 9-26 show the
disable mapping write-once register and the decoding scheme of the
bank which selectively disables PWM(s). When all bits of the disable
mapping register are set, any disable condition will disable all PWMs.
A fault can also generate a CPU interrupt. Each fault pin has its own
interrupt vector.
9.7.1 Fault Condition Input Pins
A logic high level on a fault pin disables the respective PWM(s)
determined by the bank and the disable mapp ing register . Each fault pin
incorporates a filter to assist in rejecting spurious faults. All of the
external fault pins are software-configurable to re-enable the PWMs
either with the fault pin (automatic mode) or with software (manual
mode). Each fault pin has an associated FMODE bit to control the PWM
re-enabling method. Automatic mode is selected by setting the FMODEx
bit in the fault control register. Manual mo de i s sel ected when FM ODE x
is clear.
9.7.1.1 Fault Pin Filter
Each fault pin incorporates a filter to assist in determining a genuin e fault
condition. After a fault pin has been logic low for one CPU cycle, a rising
edge (logic high) will be synchronously sampled once per CPU cycle for
two cycles. If both samples are detected logic high, the corresponding
FPIN bit and FFLAG bit will be set. The FPIN bit will remain set until the
corresponding fault pin is logic low a nd syn chr on ou sly sampled once in
the following CPU cycle.
Address: $0037
Bit 7654321Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset:11111111
Figure 9-24. PWM Disable Mapping Write-Once Register (DISMAP)