Motorola MC68HC908MR16, MC68HC908MR32 7.3 SIM Bus Clock Control and Generation

Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
92 System Integration Module (SIM) MOTOROLA
System Integration Module (SIM)
7.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 7-2. This clock can come
from either an external oscillator or from the on-chip ph ase -lo cked loop
(PLL) circuit. See Section 8. Clock Generator Module (CGM).
Figure 7-2. CGM Clock Signals
Table 7-1. Signal Name Conventions
Signal Name Description
CGMXCLK Buffered version of OSC1 from clock generator module (C GM)
CGMVCLK Phase-locked loop (PLL) circuit output
CGMOUT PLL-based or OSC1-based clock output from CGM mod ule
(Bus clock = CGMOUT divided by two)
IAB Internal address bus
IDB Internal data bus
PORRST Signal from the power-on reset module to the SIM
IRST Internal reset signal
R/W Read/write signal
PLL
OSC1 CGMXCLK
÷ 2 BUS CLOCK
GENERATORS
SIM
CGM
SIM COUNTER
PTC2
MONITOR MODE
CLOCK
SELECT
CIRCUIT
CGMVCLK
BCS
÷ 2A
BS*
CGMOUT
*When S = 1,
CGMOUT = B
USER MODE