Motorola MC68HC908MR16, MC68HC908MR32 NOTE:

Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0

164 Pulse-Width Modulator for Motor Control (PWM MC) MOTOROLA

Pulse-Width Modulator for Motor Control

The filtered fault pin’s logic state is reflected in the resp ective FPINx bit .

Any write to this bit is overwritten by the pin state. Th e FFLAGx event bit

is set with each rising edge of the respective fault pin after filtering has

been applied. To clear the FFLAGx bit, the user must write a 1 to the

corresponding FTACKx bit.

If the FINTx bit is set, a fault condition resulting in setting the

corresponding FFLAG bit will also latch a CPU interrupt request. The

interrupt request latch is not cleared until one of these actions occurs:

• The FFLAGx bit is cleared by writing a 1 to the corresponding

FTACKx bit.

• The FINTx bit is cleared. This will not clear the FFLAGx bit.

• A reset automatically clears all four interrupt latches.

If prior to a vector fetch, the interrupt request latch is cleared by one of

the actions listed, a CPU interrupt will no longer be requested. A vector

fetch does not alter the state of the PWMs, the FFLAGx event flag, or

FINTx.

NOTE: If the FFLAGx or FINTx bits are not cleared during the interrupt service

routine, the interrupt request latch will not be cleared.

9.7.1.3 Manual Mode

In manual mode, the PWM(s) are disabled immediately once a filtered

fault condition is detected (logic high). The PWM(s) remain d isabled until

software clears the corresponding FFLAGx event bit and a new PWM

cycle begins. In manual mode, the fault pins are grouped in pairs, each

pair sharing common functionality. A fault condition on pins 1 and 3 may

be cleared, allowing the PWM(s) to enable at the start of a PWM cycle

regardless of the logic level at the fault pi n. See Figure 9-28. A fault

condition on pins 2 and 4 can only be cleared, allowing the PWM(s) to

enable, if a logic low level at the fault pin is present at the start of a PWM

cycle. See Figure 9-29.

The function of the fault control and event bits is the same as in

automatic mode except that the PWMs are not re-enabled until the

FFLAGx event bit is cleared by writing to the FTACKx bit and the filtered

fault condition is cleared (logic low).

Contents

Main Page MC68HC908MR16/MC68HC908MR32 Rev. 4.0 Advance Information MOTOROLA 3 MC68HC908MR32 MC68HC908MR16 Technical Summary Revision History List of Sections Page Table of Contents Section 1. General Description Section 2. Memory Map Section 3. Random-Access Memory (RAM) Section 4. FLASH Memory Section 5. Configuration Register (CONFIG) Section 6. Central Processor Unit (CPU) Section 7. System Integration Module (SIM) Section 8. Clock Generator Module (CGM) Section 9. Pulse-Width Modulator for Motor Control (PWMMC) Section 10. Monitor ROM (MON) Section 11. Timer Interface A (TIMA) Section 12. Timer Interface B (TIMB) Section 13. Serial Peripheral Interface Module (SPI) Section 14. Serial Communications Interface Module (SCI) Section 15. Input/Output (I/O) Ports Section 16. Computer Operating Properly (COP) Section 17. External Interrupt (IRQ) Section 18. Low-Voltage Inhibit (LVI) Section 19. Analog-to-Digital Converter (ADC) Section 20. Power-On Reset (POR) Section 21. Break Module (BRK) Section 22. Electrical Specifications Section 23. Mechanical Specifications Section 24. Ordering Information Appendix A. MC68HC908MR16 List of Figures Page Page Page Page Page List of Tables List of Tables Section 1. General Description 1.1 Contents 1.2 Introduction 1.3 Features 1.4 MCU Block Diagram Advance Information MC68HC908MR16/MC68HC908MR32 Rev. 4.0 32 General Description MOTOROLA Figure 1-1. MCU Block Diagram General Description Pin Assignments MC68HC908MR16/MC68HC908MR32 Rev. 4.0 Advance Information MOTOROLA General Description 33 1.5 Pin Assignments Figure 1-2. 64-Pin QFP Pin Assignments Figure 1-3. 56-Pin SDIP Pin Assignments 34 General Description MOTOROLA Page Page Page Page Advance Information MC68HC908MR16/MC68HC908MR32 Section 2. Memory Map 2.1 Contents 2.2 Introduction 2.3 Unimplemented Memory Locations 2.4 Reserved Memory Locations 2.5 I/O Section Figure 2-1. Memory Map Figure 2-2. Control, Status, and Data Registers Summary (Sheet 1 of 10) Figure 2-2. Control, Status, and Data Registers Summary (Sheet 2 of 10) Figure 2-2. Control, Status, and Data Registers Summary (Sheet 3 of 10) Figure 2-2. Control, Status, and Data Registers Summary (Sheet 4 of 10) Figure 2-2. Control, Status, and Data Registers Summary (Sheet 5 of 10) Figure 2-2. Control, Status, and Data Registers Summary (Sheet 6 of 10) Figure 2-2. Control, Status, and Data Registers Summary (Sheet 7 of 10) Figure 2-2. Control, Status, and Data Registers Summary (Sheet 8 of 10) Figure 2-2. Control, Status, and Data Registers Summary (Sheet 9 of 10) Figure 2-2. Control, Status, and Data Registers Summary (Sheet 10 of 10) Table 2-1 is a list of vector locations. Table 2-1. Vector Addresses 2.6 Monitor ROM Table 2-1. Vector Addresses (Continued) Page Section 3. Random-Access Memory (RAM) 3.1 Contents 3.2 Introduction 3.3 Functional Description NOTE: Random-Access Memory (RAM) NOTE: Section 4. FLASH Memory 4.1 Contents 4.2 Introduction 4.3 Functional Description NOTE: 4.4 FLASH Control Register 4.5 FLASH Page Erase Operation NOTE: 4.6 FLASH Mass Erase Operation NOTE: 4.7 FLASH Program/Read Operation NOTE: FLASH Memory FLASH Program/Read Operation Figure 4-2. FLASH Programming Flowchart MC68HC908MR16/MC68HC908MR32 Rev. 4.0 Advance Information MOTOROLA FLASH Memory 63 ALGORITHM FOR PROGRAMMING A ROW (64 BYTES) OF FLASH MEMORY 4.8 FLASH Block Protection NOTE: 4.9 FLASH Block Protect Register 4.10 Wait Mode 4.11 Stop Mode NOTE: Section 5. Configuration Register (CONFIG) 5.1 Contents 5.2 Introduction 5.3 Functional Description Configuration Register (CONFIG) NOTE: 5.4 Configuration Register Page Page Section 6. Central Processor Unit (CPU) 6.1 Contents 6.2 Introduction 6.3 Features 6.4 CPU Registers Page Page Page NOTE: 6.5 Arithmetic/Logic Unit (ALU) 6.6 Low-Power Modes 6.7 CPU During Break Interrupts 6.8 Instruction Set Summary Table 6-1. Instruction Set Summary (Sheet 2 of 8) Table 6-1. Instruction Set Summary (Sheet 3 of 8) Table 6-1. Instruction Set Summary (Sheet 4 of 8) Table 6-1. Instruction Set Summary (Sheet 5 of 8) Table 6-1. Instruction Set Summary (Sheet 6 of 8) Table 6-1. Instruction Set Summary (Sheet 7 of 8) 6.9 Opcode Map See Table 6-2. Table 6-1. Instruction Set Summary (Sheet 8 of 8) MOTOROLA Central Processor Unit (CPU) 87 Opcode Map Table 6-2. Opcode Map * Page Section 7. System Integration Module (SIM) 7.1 Contents 7.2 Introduction System Integration Module (SIM) Introduction Figure 7-1. SIM Block Diagram 7.3 SIM Bus Clock Control and Generation Figure 7-2. CGM Clock Signals Table 7-1. Signal Name Conventions 7.4 Reset and System Initialization Page NOTE: Page Page 7.5 SIM Counter 7.6 Exception Control Figure 7-8. Interrupt Processing 100 System Integration Module (SIM) MOTOROLA Page NOTE: 7.7 Low-Power Mode Page 7.8 SIM Registers Page Page Page Page Section 8. Clock Generator Module (CGM) 8.1 Contents 8.2 Introduction 8.3 Features 8.4 Functional Description Figure 8-1. CGM Block Diagram 112 Clock Generator Module (CGM) MOTOROLA Page Page Page Page Page ( CAUTION: ) Page Page NOTE: 8.5 I/O Signals NOTE: 8.6 CGM Registers Page Page Page Page Page NOTE: 8.7 Interrupts NOTE: 8.8 Wait Mode 8.9 Acquisition/Lock Time Specifications Page Page Page NOTE: Section 9. Pulse-Width Modulator for Motor Control (PWMMC) 9.1 Contents Pulse-Width Modulator for Motor Control 9.2 Introduction 9.3 Features Figure 9-2. Register Summary (Sheet 1 of 3) Figure 9-2. Register Summary (Sheet 2 of 3) Figure 9-2. Register Summary (Sheet 3 of 3) 9.4 Timebase Page 9.5 PWM Generators Page NOTE: Figure 9-9. Edge-Aligned PWM Value Loading Figure 9-10. Edge-Aligned Modulus Loading 9.6 Output Control Figure 9-11. Complementary Pairing Figure 9-12. Typical AC Motor Drive Page Page Page Figure 9-15. Dead-Time at Duty Cycle Boundaries Figure 9-16. Dead-Time and Small Pu lse Widths Page NOTE: I+ I- Page Page Page NOTE: Pulse-Width Modulator for Motor Control 9.7 Fault Protection Page Figure 9-25. PWM Disabling Scheme Page NOTE: Page Pulse-Width Modulator for Motor Control 9.8 Initialization and the PWMEN Bit NOTE: Pulse-Width Modulator for Motor Control 9.9 PWM Operation in Wait Mode 9.10 Control Logic Block Page Page Page Page Page Page NOTE: Page Page Page Page Page Page Page 9.11 PWM Glossary 184 Pulse-Width Modulator for Motor Control (PWM MC) MOTOROLA Figure 9-47. PWM Load Cycle/Frequency Definition Center-Aligned Mode Edge-Aligned Mode LDFQ1:LDFQ0 = 01 Reload Every Two Cycles Section 10. Monitor ROM (MON) 10.1 Contents 10.2 Introduction 10.3 Features 10.4 Functional Description Monitor ROM (MON) Figure 10-1. Monitor Mode Circuit MC68HC908MR16/MC68HC908MR32 Rev. 4.0 Advance Information MOTOROLA Monitor ROM (MON) 187 Notes: Position A Bus clock = CGMXCLK 4 or CGMVCLK 4 Position B Bus clock = CGMXCLK 2 NOTE: Table 10-2. Monitor Mode Signal Requirements and Options Page Page Page Table 10-3. READ (Read Memory) Command Table 10-4. WRITE (Write Memory) Command NOTE: block of memory over the full 64-Kbyte memory map. Table 10-5. IREAD (Indexed Read) Command Table 10-6. IWRITE (Indexed Write) Command Table 10-7. READSP (Read Stack Pointer) Command Table 10-8. RUN (Run User Program) Command 10.5 Security NOTE: Page Page Section 11. Timer Interface A (TIMA) 11.1 Contents 11.2 Introduction 11.3 Features Timer Interface A (TIMA) Features MC68HC908MR16/MC68HC908MR32 Rev. 4.0 Advance Information MOTOROLA Timer Interface A (TIMA) 201 Figure 11-1. TIMA Block Diagram Figure 11-2. TIM I/O Register Summary Figure 11-2. TIM I/O Register Summary (Continued) 11.4 Functional Description Page Page Page Page Page NOTE: Page 11.5 Interrupts 11.6 Wait Mode 11.7 I/O Signals 11.8 I/O Registers Page Page Page Page Page Page NOTE: Page Figure 11-9. TIMA Channel Registers (TACH0H/LTACH3H/L) (Continued) Page Section 12. Timer Interface B (TIMB) 12.1 Contents 12.2 Introduction NOTE: 12.3 Features 12.4 Functional Description Timer Interface B (TIMB) NOTE: Figure 12-2. TIMB I/O Register Summary Page Page Page Page Page NOTE: Page 12.5 Interrupts 12.6 Wait Mode 12.7 I/O Signals 12.8 I/O Registers Page Page Page Page Page Page Page NOTE: Page Section 13. Serial Peripheral Interface Module (SPI) 13.1 Contents 13.2 Introduction 13.3 Features 13.4 Pin Name Conventions 13.5 Functional Description NOTE: Figure 13-1. SPI Module Block Diagram 250 Serial Peripheral Interface Module (SPI) MOTOROLA Page Page 13.6 Transmission Formats NOTE: Page Page Page Serial Peripheral Interface Module (SPI) Transmission Formats Figure 13-7. Transmission Start Delay (Master) 13.7 Error Conditions Page Page Page NOTE: 13.8 Interrupts Page 13.9 Resetting the SPI 13.10 Queuing Transmission Data Serial Peripheral Interface Module (SPI) Queuing Transmission Data 13.11 Low-Power Mode 13.12 I/O Signals Page NOTE: 13.13 I/O Registers Page Page Page Page Page NOTE: Page Section 14. Serial Communications Interface Module (SCI) 14.1 Contents 14.2 Introduction 14.3 Features Serial Communications Interface Module (SCI) 14.4 Functional Description Figure 14-1. SCI Module Block Diagram Figure 14-2. SCI I/O Register Summary Page 282 Serial Communications Interface Module (SCI) MOTOROLA Page NOTE: Serial Communications Interface Module (SCI) Figure 14-5. SCI Receiver Block Diagram Page Page Page NOTE: 14.5 Wait Mode 14.6 SCI During Break Module Interrupts 14.7 I/O Signals 14.8 I/O Registers Page Page Page Page NOTE: Page Page Page Page Page Page Page Page Table 14-7. SCI Baud Rate Selection Examples Section 15. Input/Output (I/O) Ports 15.1 Contents 15.2 Introduction NOTE: Figure 15-1. I/O Port Register Summary (Continued) 15.3 Port A NOTE: 15.4 Port B NOTE: 15.5 Port C NOTE: 15.6 Port D 15.7 Port E NOTE: 15.8 Port F NOTE: Page Page Section 16. Computer Operating Properly (COP) 16.1 Contents 16.2 Introduction Computer Operating Properly (COP) 16.3 Functional Description Figure 16-2. COP I/O Register Summary Figure 16-1. COP Block Diagram NOTE: 16.4 I/O Signals Computer Operating Properly (COP) 16.5 COP Control Register 16.6 Interrupts Page Page Section 17. External Interrupt (IRQ) 17.4 Functional Description NOTE: Figure 17-3. IRQ Interrupt Flowchart 332 External Interrupt (IRQ) MOTOROLA 17.5 IRQ Pin NOTE: 17.6 IRQ Status and Control Register Section 18. Low-Voltage Inhibit (LVI) 18.1 Contents 18.2 Introduction 18.3 Features Low-Voltage Inhibit (LVI) 18.4 Functional Description Page Low-Voltage Inhibit (LVI) NOTE: 18.5 LVI Status and Control Register NOTE: 18.6 LVI Interrupts 18.7 Wait Mode Page Section 19. Analog-to-Digital Converter (ADC) 19.1 Contents 19.2 Introduction 19.3 Features 19.4 Functional Description Page Page Page NOTE: 19.5 Interrupts 19.6 Wait Mode 19.7 I/O Signals NOTE: 19.8 I/O Registers NOTE: Table 19-1. Mux Channel Select Page Page Page Page Page Section 20. Power-On Reset (POR) 20.1 Contents 20.2 Introduction 20.3 Functional Description Page Section 21. Break Module (BRK) 21.1 Contents 21.2 Introduction 21.3 Features 21.4 Functional Description Figure 21-1. Break Module Block Diagram Figure 21-2. I/O Register Summary 21.5 Low-Power Modes 21.6 Break Module Registers Page Page Page Section 22. Electrical Specifications 22.1 Contents 22.2 Introduction 22.3 Absolute Maximum Ratings NOTE: 22.4 Functional Operating Range 22.5 Thermal Characteristics 370 Electrical Specifications MOTOROLA 22.6 DC Electrical Characteristics (VDD = 5.0 Vdc 10%) 22.7 FLASH Memory Characteristics 22.8 Control Timing (VDD = 5.0 Vdc 10%) 22.9 Serial Peripheral Interface Characteristics (V Figure 22-1. SPI Master Timing 374 Electrical Specifications MOTOROLA a) SPI Master Timing (CPHA = 0) b) SPI Master Timing (CPHA = 1) Electrical Specifications Serial Peripheral Interface Characteristics (VDD = 5.0 Vdc 10%) Figure 22-2. SPI Slave Timing MC68HC908MR16/MC68HC908MR32 Rev. 4.0 Advance Information MOTOROLA Electrical Specifications 375 a) SPI Slave Timing (CPHA = 0) b) SPI Slave Timing (CPHA = 1) 22.10 TImer Interface Module Characteristics 22.11 Clock Generation Module Component Specifications 22.12 CGM Operating Conditions 22.13 CGM Acquisition/Lock Time Specifications 22.14 Analog-to-Digital Converter (ADC) Characteristics Section 23. Mechanical Specifications 23.1 Contents 23.2 Introduction 380 Mechanical Specifications MOTOROLA Mechanical Specifications 23.3 64-Pin Plastic Quad Flat Pack (QFP) Figure 23-1. MC68HC908MR32FU Mechanical Specifications 56-Pin Shrink Dual In-Line Package (SDIP) MC68HC908MR16/MC68HC908MR32 Rev. 4.0 Advance Information MOTOROLA Mechanical Specifications 381 23.4 56-Pin Shrink Dual In-Line Package (SDIP) Figure 23-2. MC68HC908MR32B Page Section 24. Ordering Information 24.1 Contents 24.2 Introduction This section contains instructions for ordering the MC68HC908MR16 and MC68HC908MR32. 24.3 Order Numbers Page Appendix A. MC68HC908MR16 386 MC68HC908MR16 MOTOROLA MC68HC908MR16 A.3 Memory Map Figure A-1. MC68HC908MR16 Memory Map Page MC68HC908MR32/D REV 4 MC68HC08AS60 Technical Data How to Reach Us: