Special function registers table P89LPC907 | Philips P89LPC906

Philips Semiconductors

User’s Manual - Preliminary -

GENERAL DESCRIPTION

P89LPC906/907/908

Table 2: Special function registers table - P89LPC907

Name

Description

SFR

Bit Functions and Addresses

Reset Value

Address

MSB

LSB

Hex

Binary

E7

E6

E5

E4

E3

E2

E1

E0

ACC*

Accumulator

E0H

00H

00000000

00H1

AUXR1#

Auxiliary Function Register

A2H

-

-

-

-

SRST

0

-

DPS

000000x0

F7

F6

F5

F4

F3

F2

F1

F0

B*

B Register

F0H

00H

00000000

BRGR0#§

Baud Rate Generator Rate Low

BEH

00H

00000000

BRGR1#§

Baud Rate Generator Rate High

BFH

00H

00000000

BRGCON#

Baud Rate Generator Control

BDH

-

-

-

-

-

-

SBRGS

BRGEN

00H

xxxxxx00

00H1

xx000000

CMP1#

Comparator 1 Control Register

ACH

-

-

CE1

-

CN1

OE1

CO1

CMF1

DIVM#

CPU Clock Divide-by-M Control

95H

00H

00000000

DPTR

Data Pointer (2 bytes)

DPH

Data Pointer High

83H

00H

00000000

DPL

Data Pointer Low

82H

00H

00000000

FMADRH#

Program Flash Address High

E7H

00H

00000000

FMADRL#

Program Flash Address Low

E6H

00H

00000000

Program Flash Control (Read)

BUSY

-

-

-

HVA

HVE

SV

OI

70H

01110000

FMCON#

E4H

Program Flash Control (Write)

FMCMD.

FMCMD.

FMCMD.

FMCMD.

FMCMD.

FMCMD.

FMCMD.

FMCMD.

7

6

5

4

3

2

1

0

FMDATA#

Program Flash Data

E5H

00H

00000000

IEN0*

Interrupt Enable 0

A8H

EA

EWDRT

EBO

ES

ET1

-

ET0

-

00H

00000000

EF

EE

ED

EC

EB

EA

E9

E8

00H1

00x00000

IEN1*#

Interrupt Enable 1

E8H

-

EST

-

-

-

EC

EKBI

-

BF

BE

BD

BC

BB

BA

B9

B8

00H1

x0000000

IP0*

Interrupt Priority 0

B8H

-

PWDRT

PBO

PS

PT1

-

PT0

-

IP0H#

Interrupt Priority 0 High

B7H

-

PWDRT

PBOH

PSH

PT1H

-

PT0H

-

00H1

x0000000

H

FF

FE

FD

FC

FB

FA

F9

F8

00H1

00x00000

IP1*#

Interrupt Priority 1

F8H

-

PST

-

-

-

PC

PKBI

-

00H1

00x00000

IP1H#

Interrupt Priority 1 High

F7H

-

PSTH

-

-

-

PCH

PKBIH

-

KBCON#

Keypad Control Register

94H

-

-

-

-

-

-

PATN_S

KBIF

00H1

xxxxxx00

EL

2003 Dec 8

18

Image 18

Philips P89LPC906, P89LPC908 user manual Special function registers table P89LPC907

Contents

User Manual Table of Contents Brownout Detection Power-On Detection Power Reduction Modes Power-On reset code execution 103 List of Figures List of Figures PIN Configurations P89LPC906 Logic Symbols Product Comparison CPU Block Diagram P89LPC906KB Code Flash Oscillator Divider Byte Data RAM Block Diagram P89LPC907Uart Clock Block Diagram P89LPC908 Data RAM Port PIN Descriptions P89LPC906 TxD PIN Descriptions P89LPC907P1.0 P1.2 P1.1 PIN Descriptions P89LPC908Keyboard Input P1.0 P1.5 RxD Special function registers Special function registers table P89LPC906 MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 SFR Memory OrganizationData Code CPU Clock Oscclk Enhanced CPUClock Definitions LOW Speed Oscillator Option P89LPC906 ON-CHIP RC Oscillator Option Oscillator Option SELECTION- P89LPC906Clock Output P89LPC906 Watchdog Oscillator Option External Clock Input Option P89LPC906 CPU Clock Cclk Wakeup DelayBIT Symbol Function CPU Clock Cclk Modification Divm Register Med freq LOW Power Select P89LPC906High freq Low freq CPU Clocks Summary of Interrupts P89LPC906 Description Flag Bits Address Enable Bits Priority RankingInterrupt Priority Structure Interrupt Arbitration Summary of Interrupts P89LPC907,P89LPC908 Description External Interrupt InputsExternal Interrupt PIN Glitch Suppression TI & RI Bopd EBO Rtcf Kbif Interrupts Number of I/O Pins Available Clock Source Reset Option Port ConfigurationsQUASI-BIDIRECTIONAL Output Configuration RST Open Drain Output Configuration Port latch data Port 0 Analog Functions INPUT-ONLY ConfigurationPUSH-PULL Output Configuration Strong Port latch data Port pin Input data Glitch rejection Port Output Configuration P89LPC906 Port Output Configuration P89LPC907Port Output Configuration P89LPC908 Ports Ports TMOD.6 TmodTMOD.7 TMOD.3 Tamod P89LPC907 Overflows. ModeMode TAMOD.7-1 Tcon T0C/T = Overflow PclkT0C/T = Overflow TLn THn TFn Interrupt T0 Pin THn TFn Timer Overflow Toggle Output P89LPC907 Pclk TL0TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source Xclk FOSC2 FOSC1 FOSC0 RTCS10UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency Divm Cclk Undefined RC Oscillator/DIVMWDT Oscillator/DIVM External clock/DIVM Reset Sources Affecting the REAL-TIME Clock Changing RTCS1-0REAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection POWER-ON Detection Power Reduction ModesBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Uart Modes Updating the BRGR1 and BRGR0 Sfrs SFR SpaceBaud Rate Generator and Selection SFR Locations for UARTs Framing Error Break DetectBrgcon Scon More about Uart Mode Sstat Serial Port Mode 0 Double Buffering Must Be Disabled More about Uart Modes 2 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 PCON.6 RB8 SMOD0 Double Buffering Double Buffering in Different Modes 9TH BIT BIT 8 in Double Buffering Modes 1, 2 Transmission with and without Double Buffering Multiprocessor Communications Automatic Address Recognition Uart Uart POWER-ON Reset Code Execution Block Diagram of Reset Rstsrc Comparator Configuration Comparator Interrupt Comparator and Power Reduction ModesInternal Reference Voltage CIN1A CO1 CMP1 Cmpref Comparator Configuration Example Analog Comparators Kbpatn Kbcon Kbmask Watchdog timer configuration Watchdog FunctionWdte Wdse Function Feed Sequence Wdcon P89LPC906/907/908 Watchdog Timeout Values PRE2-PRE0 Watchdog Watchdog Timer in Timer ModePrescaler Reset Pclk Control register Prescaler Power Down OperationWatchdog Clock Source CLK Watchdog Timer Watchdog Timer Software Reset Dual Data PointersAUXR1 MOVXA, @DPTR MOVCA, @A+DPTRMove code byte relative to Dptr to the accumulator MOVX@DPTR, a General Description FeaturesUsing Flash AS Data Storage Introduction to IAP-LITE Flash Program Memory Fmcon Accessing Additional Flash Elements Assembly language routine to erase/program all or part of a ERASE-PROGRAMMING Additional Flash Elements Reading Additional Flash ElementsUCFG1 Fmadrl Conf User Configuration Bytes UCFG1P89LPC906 Address xxxxh User Security BytesSECx Unprogrammed value 00h Bootvec Bootstat Arithmetic Logical Mnemonic Description Bytes Cycles Hex Code Data Transfer Boolean Branching D8-DF RetiB8-BF Miscellaneous 2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908