Philips P89LPC907, P89LPC906, P89LPC908 manual

Philips Semiconductors

User’s Manual - Preliminary -

GENERAL DESCRIPTION

P89LPC906/907/908

Name

Description

SFR

Bit Functions and Addresses

Reset Value

Address

MSB

LSB

Hex

Binary

TH0

Timer 0 High

8CH

00H

00000000

TH1

Timer 1 High

8DH

00H

00000000

TL0

Timer 0 Low

8AH

00H

00000000

TL1

Timer 1 Low

8BH

00H

00000000

TMOD

Timer 0 and 1 Mode

89H

-

-

T1M1

T1M0

-

-

T0M1

T0M0

00H

00000000

TRIM#

Internal Oscillator Trim Register

96H

-

-

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

Notes 4,5

WDCON#

Watchdog Control Register

A7H

PRE2

PRE1

PRE0

-

-

WDRUN

WDTOF

WDCLK

Notes 3,5

WDL#

Watchdog Load

C1H

FFH

11111111

WFEED1#

Watchdog Feed 1

C2H

WFEED2#

Watchdog Feed 2

C3H

2003 Dec 8

20

Image 20

Philips P89LPC907, P89LPC906, P89LPC908 user manual TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON#

Contents

User Manual Table of Contents Brownout Detection Power-On Detection Power Reduction Modes Power-On reset code execution 103 List of Figures List of Figures PIN Configurations P89LPC906 Logic Symbols Product Comparison Block Diagram P89LPC906 KB Code FlashCPU Oscillator Divider Block Diagram P89LPC907 UartByte Data RAM Clock Block Diagram P89LPC908 Data RAM Port PIN Descriptions P89LPC906 PIN Descriptions P89LPC907 P1.0TxD P1.2 PIN Descriptions P89LPC908 Keyboard Input P1.0 P1.5P1.1 RxD Special function registers Special function registers table P89LPC906 MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Memory Organization DataSFR Code Enhanced CPU Clock DefinitionsCPU Clock Oscclk LOW Speed Oscillator Option P89LPC906 Oscillator Option SELECTION- P89LPC906 Clock Output P89LPC906ON-CHIP RC Oscillator Option Watchdog Oscillator Option CPU Clock Cclk Wakeup Delay BIT Symbol FunctionExternal Clock Input Option P89LPC906 CPU Clock Cclk Modification Divm Register LOW Power Select P89LPC906 High freqMed freq Low freq CPU Clocks Flag Bits Address Enable Bits Priority Ranking Interrupt Priority StructureSummary of Interrupts P89LPC906 Description Interrupt Arbitration External Interrupt Inputs External Interrupt PIN Glitch SuppressionSummary of Interrupts P89LPC907,P89LPC908 Description TI & RI Bopd EBO Rtcf Kbif Interrupts Port Configurations QUASI-BIDIRECTIONAL Output ConfigurationNumber of I/O Pins Available Clock Source Reset Option RST Open Drain Output Configuration Port latch data INPUT-ONLY Configuration PUSH-PULL Output ConfigurationPort 0 Analog Functions Strong Port latch data Port pin Input data Glitch rejection Port Output Configuration P89LPC908 Port Output Configuration P89LPC906Port Output Configuration P89LPC907 Ports Ports Tmod TMOD.7TMOD.6 TMOD.3 Overflows. Mode ModeTamod P89LPC907 TAMOD.7-1 Tcon Pclk T0C/T = Overflow TLn THn TFn Interrupt T0 PinT0C/T = Overflow THn TFn TR0 ENT0 Pclk TH0 Timer Overflow Toggle Output P89LPC907Pclk TL0 Timers 0 REAL-TIME Clock Source FOSC2 FOSC1 FOSC0 RTCS10 UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock FrequencyXclk Divm Cclk RC Oscillator/DIVM WDT Oscillator/DIVMUndefined External clock/DIVM REAL-TIME Clock INTERRUPT/WAKE UP Reset Sources Affecting the REAL-TIME ClockChanging RTCS1-0 Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Brownout Options POWER-ON DetectionPower Reduction Modes Power Reduction Modes Pcon Pcona Power Monitoring Functions Uart Modes SFR Space Baud Rate Generator and SelectionUpdating the BRGR1 and BRGR0 Sfrs SFR Locations for UARTs Brgcon Framing ErrorBreak Detect Scon More about Uart Mode Sstat Serial Port Mode 0 Double Buffering Must Be Disabled Framing Error and RI in Modes 2 and 3 with SM2 = FE and RI when SM2 = 1 in Modes 2More about Uart Modes 2 PCON.6 RB8 SMOD0 Double Buffering Double Buffering in Different Modes 9TH BIT BIT 8 in Double Buffering Modes 1, 2 Transmission with and without Double Buffering Multiprocessor Communications Automatic Address Recognition Uart Uart POWER-ON Reset Code Execution Block Diagram of Reset Rstsrc Comparator Configuration Comparator and Power Reduction Modes Internal Reference VoltageComparator Interrupt CIN1A CO1 CMP1 Cmpref Comparator Configuration Example Analog Comparators Kbpatn Kbcon Kbmask Wdte Wdse Function Watchdog timer configurationWatchdog Function Feed Sequence Wdcon P89LPC906/907/908 Watchdog Timeout Values PRE2-PRE0 Watchdog Timer in Timer Mode Prescaler Reset PclkWatchdog Control register Power Down Operation Watchdog Clock SourcePrescaler CLK Watchdog Timer Watchdog Timer AUXR1 Software ResetDual Data Pointers MOVCA, @A+DPTR Move code byte relative to Dptr to the accumulatorMOVXA, @DPTR MOVX@DPTR, a Features Using Flash AS Data StorageGeneral Description Introduction to IAP-LITE Flash Program Memory Fmcon Accessing Additional Flash Elements Assembly language routine to erase/program all or part of a UCFG1 ERASE-PROGRAMMING Additional Flash ElementsReading Additional Flash Elements Fmadrl Conf P89LPC906 User Configuration BytesUCFG1 User Security Bytes SECxAddress xxxxh Unprogrammed value 00h Bootvec Bootstat Arithmetic Logical Mnemonic Description Bytes Cycles Hex Code Data Transfer Boolean Branching Reti B8-BFD8-DF Miscellaneous 2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908