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Philips P89LPC908, P89LPC906, P89LPC907 user manual 9TH BIT BIT 8 in Double Buffering Modes 1, 2

Models: P89LPC907 P89LPC908 P89LPC906

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Philips Semiconductors	User’s Manual - Preliminary -

UART	P89LPC906/907/908

TxD

Write to

SBUF

Tx Interrupt

Single Buffering (DBMOD/SSTAT.7 = 0), Early Interrupt (INTLO/SSTAT.6 = 0) is Shown

TxD

Write to

SBUF

Tx Interrupt

Double Buffering (DBMOD/SSTAT.7 = 1), Early Interrupt (INTLO/SSTAT.6 = 0) is Shown, No End-

ing Tx Interrupt (DBISEL/SnSTAT.4 = 0)

TxD

Write to

SBUF

Tx Interrupt

Double Buffering (DBMOD/SSTAT.7 = 1), Early Interrupt (INTLO/SSTAT.6 = 0) is Shown, With

Ending Tx Interrupt (DBISEL/SSTAT.4 = 1)

Figure 8-8: Transmission with and without Double Buffering

THE 9TH BIT (BIT 8) IN DOUBLE BUFFERING (MODES 1, 2 AND 3)

If double buffering is disabled (DBMOD, i.e. SSTAT.7 = 0), TB8 can be written before or after SBUF is written, provided TB8 is updated before that TB8 is shifted out. TB8 must not be changed again until after TB8 shifting has been completed, as indicated by the Tx interrupt.

If double buffering is enabled, TB8 MUST be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data. The operation described in the section "Transmit Interrupts with Double Buffering Enabled (Modes 1, 2 and 3)" becomes as follows:

1.The double buffer is empty initially.

2.The CPU writes to TB8.

3.The CPU writes to SBUF.

4.The SBUF/TB8 data is loaded to the shift register and a Tx interrupt is generated immediately.

5.If there is more data, go to 7, else continue on 6.

6.If there is no more data, then:

-If DBISEL is ’0’, no more interrupt will occur.

-If DBISEL is ’1’ and INTLO is ’0’, a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter (which is also the last data).

2003 Dec 8

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Image 67

Philips P89LPC908, P89LPC906 9TH BIT BIT 8 in Double Buffering Modes 1, 2, Transmission with and without Double Buffering

Contents

User Manual Table of Contents Power-On reset code execution Brownout Detection Power-On Detection Power Reduction Modes103 List of Figures List of Figures P89LPC906 PIN ConfigurationsProduct Comparison Logic SymbolsOscillator Divider Block Diagram P89LPC906KB Code Flash CPUClock Block Diagram P89LPC907Uart Byte Data RAMData RAM Port Block Diagram P89LPC908PIN Descriptions P89LPC906 P1.2 PIN Descriptions P89LPC907P1.0 TxDRxD PIN Descriptions P89LPC908Keyboard Input P1.0 P1.5 P1.1Special function registers table P89LPC906 Special function registersMSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Code Memory OrganizationData SFRLOW Speed Oscillator Option P89LPC906 Enhanced CPUClock Definitions CPU Clock OscclkWatchdog Oscillator Option Oscillator Option SELECTION- P89LPC906Clock Output P89LPC906 ON-CHIP RC Oscillator OptionCPU Clock Cclk Modification Divm Register CPU Clock Cclk Wakeup DelayBIT Symbol Function External Clock Input Option P89LPC906Low freq LOW Power Select P89LPC906High freq Med freqCPU Clocks Interrupt Arbitration Flag Bits Address Enable Bits Priority RankingInterrupt Priority Structure Summary of Interrupts P89LPC906 DescriptionTI & RI External Interrupt InputsExternal Interrupt PIN Glitch Suppression Summary of Interrupts P89LPC907,P89LPC908 DescriptionBopd EBO Rtcf Kbif Interrupts RST Port ConfigurationsQUASI-BIDIRECTIONAL Output Configuration Number of I/O Pins Available Clock Source Reset OptionPort latch data Open Drain Output ConfigurationStrong Port latch data Port pin Input data Glitch rejection INPUT-ONLY ConfigurationPUSH-PULL Output Configuration Port 0 Analog FunctionsPort Output Configuration P89LPC907 Port Output Configuration P89LPC906Port Output Configuration P89LPC908 Ports Ports TMOD.3 TmodTMOD.7 TMOD.6TAMOD.7-1 Overflows. ModeMode Tamod P89LPC907Tcon THn TFn PclkT0C/T = Overflow TLn THn TFn Interrupt T0 Pin T0C/T = OverflowPclk TL0 Timer Overflow Toggle Output P89LPC907TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source Divm Cclk FOSC2 FOSC1 FOSC0 RTCS10UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency XclkExternal clock/DIVM RC Oscillator/DIVMWDT Oscillator/DIVM UndefinedChanging RTCS1-0 Reset Sources Affecting the REAL-TIME ClockREAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Power Reduction Modes POWER-ON DetectionBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Modes UartSFR Locations for UARTs SFR SpaceBaud Rate Generator and Selection Updating the BRGR1 and BRGR0 SfrsBreak Detect Framing ErrorBrgcon Scon Sstat More about Uart ModeSerial Port Mode 0 Double Buffering Must Be Disabled PCON.6 RB8 SMOD0 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 More about Uart Modes 2Double Buffering in Different Modes Double BufferingTransmission with and without Double Buffering 9TH BIT BIT 8 in Double Buffering Modes 1, 2Automatic Address Recognition Multiprocessor CommunicationsUart Uart Block Diagram of Reset POWER-ON Reset Code ExecutionRstsrc Comparator Configuration CIN1A CO1 CMP1 Cmpref Comparator and Power Reduction ModesInternal Reference Voltage Comparator InterruptComparator Configuration Example Analog Comparators Kbcon KbpatnKbmask Watchdog Function Watchdog timer configurationWdte Wdse Function Feed Sequence Wdcon PRE2-PRE0 P89LPC906/907/908 Watchdog Timeout ValuesControl register Watchdog Timer in Timer ModePrescaler Reset Pclk WatchdogCLK Power Down OperationWatchdog Clock Source PrescalerWatchdog Timer Watchdog Timer Dual Data Pointers Software ResetAUXR1 MOVX@DPTR, a MOVCA, @A+DPTRMove code byte relative to Dptr to the accumulator MOVXA, @DPTRIntroduction to IAP-LITE FeaturesUsing Flash AS Data Storage General DescriptionFlash Program Memory Fmcon Assembly language routine to erase/program all or part of a Accessing Additional Flash ElementsReading Additional Flash Elements ERASE-PROGRAMMING Additional Flash ElementsUCFG1 Fmadrl Conf UCFG1 User Configuration BytesP89LPC906 Unprogrammed value 00h User Security BytesSECx Address xxxxhBootstat BootvecLogical ArithmeticData Transfer Mnemonic Description Bytes Cycles Hex CodeBranching BooleanMiscellaneous RetiB8-BF D8-DF2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908