FOSC2 FOSC1 FOSC0 RTCS10, Xclk, Divm Cclk | Philips P89LPC906

Philips Semiconductors	User’s Manual - Preliminary -

REAL-TIME CLOCK/SYSTEM TIMER	P89LPC906/907/908

			Power-On
			Reset
RTCH		RTCL	RTC Reset		XTAL2 XTAL1
Reload on underflow
					Low freq.
					Med. freq.
MSB		LSB	7-bit prescaler		High freq.
	23-bit down counter		÷ 128		CCLK
Wake up from					Int. Osc’s
Wake up from
Power-down		RTCF	RTCEN	RTCS1	RTCS2
		RTCF	RTCEN	RTCS1	RTCS2
Interrupt	ERTC	RTC underflow flag	RTC Enable	RTC clk select
if enabled
(shared w. WDT)

Figure 6-1: Real-time clock/system timer Block Diagram

Table 6-1: Real-time Clock/System Timer Clock Source - P89LPC906

FOSC2	FOSC1	FOSC0	RTCS1:0
(UCFG1.2)	(UCFG1.1)	(UCFG1.0)	RTCS1:0	CCLK Frequency	RTC Clock Frequency

			00		High frequency crystal

			01
			01		(XCLK)
0	0	0		High frequency crystal/DIVM	(XCLK)
0	0	0	10	High frequency crystal/DIVM

			11		High frequency crystal/DIVM
			11		(CCLK)
					(CCLK)

			00		Medium frequency crystal

			01
			01		(XCLK)
0	0	1		Medium frequency crystal/DIVM	(XCLK)
0	0	1	10	Medium frequency crystal/DIVM

			11		Medium frequency crystal/
			11		DIVM (CCLK)
					DIVM (CCLK)

			00		Low frequency crystal

			01
			01		(XCLK)
0	1	0		Low frequency crystal/DIVM	(XCLK)
0	1	0	10	Low frequency crystal/DIVM

			11		Low frequency crystal/DIVM
			11		(CCLK)
					(CCLK)

2003 Dec 8

48

Image 48

Philips P89LPC906 FOSC2 FOSC1 FOSC0 RTCS10, UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency, Xclk, Divm Cclk

Contents

User Manual Table of Contents Brownout Detection Power-On Detection Power Reduction Modes Power-On reset code execution 103 List of Figures List of Figures PIN Configurations P89LPC906 Logic Symbols Product Comparison Block Diagram P89LPC906 KB Code FlashCPU Oscillator Divider Block Diagram P89LPC907 UartByte Data RAM Clock Block Diagram P89LPC908 Data RAM Port PIN Descriptions P89LPC906 PIN Descriptions P89LPC907 P1.0TxD P1.2 PIN Descriptions P89LPC908 Keyboard Input P1.0 P1.5P1.1 RxD Special function registers Special function registers table P89LPC906 MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Memory Organization DataSFR Code Enhanced CPU Clock DefinitionsCPU Clock Oscclk LOW Speed Oscillator Option P89LPC906 Oscillator Option SELECTION- P89LPC906 Clock Output P89LPC906ON-CHIP RC Oscillator Option Watchdog Oscillator Option CPU Clock Cclk Wakeup Delay BIT Symbol FunctionExternal Clock Input Option P89LPC906 CPU Clock Cclk Modification Divm Register LOW Power Select P89LPC906 High freqMed freq Low freq CPU Clocks Flag Bits Address Enable Bits Priority Ranking Interrupt Priority StructureSummary of Interrupts P89LPC906 Description Interrupt Arbitration External Interrupt Inputs External Interrupt PIN Glitch SuppressionSummary of Interrupts P89LPC907,P89LPC908 Description TI & RI Bopd EBO Rtcf Kbif Interrupts Port Configurations QUASI-BIDIRECTIONAL Output ConfigurationNumber of I/O Pins Available Clock Source Reset Option RST Open Drain Output Configuration Port latch data INPUT-ONLY Configuration PUSH-PULL Output ConfigurationPort 0 Analog Functions Strong Port latch data Port pin Input data Glitch rejection Port Output Configuration P89LPC906 Port Output Configuration P89LPC907Port Output Configuration P89LPC908 Ports Ports Tmod TMOD.7TMOD.6 TMOD.3 Overflows. Mode ModeTamod P89LPC907 TAMOD.7-1 Tcon Pclk T0C/T = Overflow TLn THn TFn Interrupt T0 PinT0C/T = Overflow THn TFn Timer Overflow Toggle Output P89LPC907 Pclk TL0TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source FOSC2 FOSC1 FOSC0 RTCS10 UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock FrequencyXclk Divm Cclk RC Oscillator/DIVM WDT Oscillator/DIVMUndefined External clock/DIVM Reset Sources Affecting the REAL-TIME Clock Changing RTCS1-0REAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection POWER-ON Detection Power Reduction ModesBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Uart Modes SFR Space Baud Rate Generator and SelectionUpdating the BRGR1 and BRGR0 Sfrs SFR Locations for UARTs Framing Error Break DetectBrgcon Scon More about Uart Mode Sstat Serial Port Mode 0 Double Buffering Must Be Disabled Framing Error and RI in Modes 2 and 3 with SM2 = FE and RI when SM2 = 1 in Modes 2More about Uart Modes 2 PCON.6 RB8 SMOD0 Double Buffering Double Buffering in Different Modes 9TH BIT BIT 8 in Double Buffering Modes 1, 2 Transmission with and without Double Buffering Multiprocessor Communications Automatic Address Recognition Uart Uart POWER-ON Reset Code Execution Block Diagram of Reset Rstsrc Comparator Configuration Comparator and Power Reduction Modes Internal Reference VoltageComparator Interrupt CIN1A CO1 CMP1 Cmpref Comparator Configuration Example Analog Comparators Kbpatn Kbcon Kbmask Watchdog timer configuration Watchdog FunctionWdte Wdse Function Feed Sequence Wdcon P89LPC906/907/908 Watchdog Timeout Values PRE2-PRE0 Watchdog Timer in Timer Mode Prescaler Reset PclkWatchdog Control register Power Down Operation Watchdog Clock SourcePrescaler CLK Watchdog Timer Watchdog Timer Software Reset Dual Data PointersAUXR1 MOVCA, @A+DPTR Move code byte relative to Dptr to the accumulatorMOVXA, @DPTR MOVX@DPTR, a Features Using Flash AS Data StorageGeneral Description Introduction to IAP-LITE Flash Program Memory Fmcon Accessing Additional Flash Elements Assembly language routine to erase/program all or part of a ERASE-PROGRAMMING Additional Flash Elements Reading Additional Flash ElementsUCFG1 Fmadrl Conf User Configuration Bytes UCFG1P89LPC906 User Security Bytes SECxAddress xxxxh Unprogrammed value 00h Bootvec Bootstat Arithmetic Logical Mnemonic Description Bytes Cycles Hex Code Data Transfer Boolean Branching Reti B8-BFD8-DF Miscellaneous 2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908