More about Uart Modes 2, PCON.6 RB8 SMOD0 | Philips P89LPC907

Philips Semiconductors	User’s Manual - Preliminary -

UART	P89LPC906/907/908

MORE ABOUT UART MODES 2 AND 3

Reception is the same as in Mode 1.

The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. (a) RI = 0, and (b) Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF.

TX Clock

Write to SBUF

Shift

TxD

D0

D1

D2

D3

D4

D5

D6

D7

Transmit

Bit

TB8

Stop Bit

TI

INTLO = 0

INTLO = 1

RX Clock

RxD

÷ 16 Reset

Start Bit

D0

D1

D2

D3

D4

D5

D6

D7

RB8

Stop Bit

Shift

Receive

RI

SMOD0 = 0

SMOD0 = 1

Figure 8-7: Serial Port Mode 2 or 3 (Only Single Transmit Buffering Case Is Shown)

FRAMING ERROR AND RI IN MODES 2 AND 3 WITH SM2 = 1

If SM2 = 1 in modes 2 and 3, RI and FE behave as in the following table.

	Mode	PCON.6	RB8	RI	FE
	Mode	(SMOD0)	RB8	RI	FE
		(SMOD0)

			0	No RI when RB8 = 0	Occurs during STOP bit
	2	0
	2	0	1	Similar to Figure 8-7, with SMOD0 = 0, RI	Occurs during STOP bit
			1	occurs during RB8, one bit before FE	Occurs during STOP bit
				occurs during RB8, one bit before FE

			0	No RI when RB8 = 0	Will NOT occur
	3	1
	3	1	1	Similar to Figure 8-7, with SMOD0 = 1, RI	Occurs during STOP bit
			1	occurs during STOP bit	Occurs during STOP bit
				occurs during STOP bit

Table 8-3: FE and RI when SM2 = 1 in Modes 2 and 3.

BREAK DETECT

A break is detected when 11 consecutive bits are sensed low and is reported in the status register (SSTAT). For Mode 1, this consists of the start bit, 8 data bits, and two stop bit times. For Modes 2 & 3, this consists of the start bit, 9 data bits, and one stop bit. The break detect bit is cleared in software or by a reset. The break detect can be used to reset the device. This occurs if the UART is enabled and the the EBRR bit (AUXR1.6) is set and a break occurs.

2003 Dec 8

65

Image 65

Philips P89LPC907, P89LPC906 More about Uart Modes 2, Framing Error and RI in Modes 2 and 3 with SM2 =, PCON.6 RB8 SMOD0

Contents

User Manual Table of Contents Power-On reset code execution Brownout Detection Power-On Detection Power Reduction Modes 103 List of Figures List of Figures P89LPC906 PIN Configurations Product Comparison Logic Symbols KB Code Flash Block Diagram P89LPC906CPU Oscillator Divider Uart Block Diagram P89LPC907Byte Data RAM Clock Data RAM Port Block Diagram P89LPC908 PIN Descriptions P89LPC906 P1.0 PIN Descriptions P89LPC907TxD P1.2 Keyboard Input P1.0 P1.5 PIN Descriptions P89LPC908P1.1 RxD Special function registers table P89LPC906 Special function registers MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Data Memory OrganizationSFR Code Clock Definitions Enhanced CPUCPU Clock Oscclk LOW Speed Oscillator Option P89LPC906 Clock Output P89LPC906 Oscillator Option SELECTION- P89LPC906ON-CHIP RC Oscillator Option Watchdog Oscillator Option BIT Symbol Function CPU Clock Cclk Wakeup DelayExternal Clock Input Option P89LPC906 CPU Clock Cclk Modification Divm Register High freq LOW Power Select P89LPC906Med freq Low freq CPU Clocks Interrupt Priority Structure Flag Bits Address Enable Bits Priority RankingSummary of Interrupts P89LPC906 Description Interrupt Arbitration External Interrupt PIN Glitch Suppression External Interrupt InputsSummary of Interrupts P89LPC907,P89LPC908 Description TI & RI Bopd EBO Rtcf Kbif Interrupts QUASI-BIDIRECTIONAL Output Configuration Port ConfigurationsNumber of I/O Pins Available Clock Source Reset Option RST Port latch data Open Drain Output Configuration PUSH-PULL Output Configuration INPUT-ONLY ConfigurationPort 0 Analog Functions Strong Port latch data Port pin Input data Glitch rejection Port Output Configuration P89LPC908 Port Output Configuration P89LPC906Port Output Configuration P89LPC907 Ports Ports TMOD.7 TmodTMOD.6 TMOD.3 Mode Overflows. ModeTamod P89LPC907 TAMOD.7-1 Tcon T0C/T = Overflow TLn THn TFn Interrupt T0 Pin PclkT0C/T = Overflow THn TFn TR0 ENT0 Pclk TH0 Timer Overflow Toggle Output P89LPC907Pclk TL0 Timers 0 REAL-TIME Clock Source UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency FOSC2 FOSC1 FOSC0 RTCS10Xclk Divm Cclk WDT Oscillator/DIVM RC Oscillator/DIVMUndefined External clock/DIVM REAL-TIME Clock INTERRUPT/WAKE UP Reset Sources Affecting the REAL-TIME ClockChanging RTCS1-0 Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Brownout Options POWER-ON DetectionPower Reduction Modes Power Reduction Modes Pcon Pcona Power Monitoring Functions Modes Uart Baud Rate Generator and Selection SFR SpaceUpdating the BRGR1 and BRGR0 Sfrs SFR Locations for UARTs Brgcon Framing ErrorBreak Detect Scon Sstat More about Uart Mode Serial Port Mode 0 Double Buffering Must Be Disabled FE and RI when SM2 = 1 in Modes 2 Framing Error and RI in Modes 2 and 3 with SM2 =More about Uart Modes 2 PCON.6 RB8 SMOD0 Double Buffering in Different Modes Double Buffering Transmission with and without Double Buffering 9TH BIT BIT 8 in Double Buffering Modes 1, 2 Automatic Address Recognition Multiprocessor Communications Uart Uart Block Diagram of Reset POWER-ON Reset Code Execution Rstsrc Comparator Configuration Internal Reference Voltage Comparator and Power Reduction ModesComparator Interrupt CIN1A CO1 CMP1 Cmpref Comparator Configuration Example Analog Comparators Kbcon Kbpatn Kbmask Wdte Wdse Function Watchdog timer configurationWatchdog Function Feed Sequence Wdcon PRE2-PRE0 P89LPC906/907/908 Watchdog Timeout Values Prescaler Reset Pclk Watchdog Timer in Timer ModeWatchdog Control register Watchdog Clock Source Power Down OperationPrescaler CLK Watchdog Timer Watchdog Timer AUXR1 Software ResetDual Data Pointers Move code byte relative to Dptr to the accumulator MOVCA, @A+DPTRMOVXA, @DPTR MOVX@DPTR, a Using Flash AS Data Storage FeaturesGeneral Description Introduction to IAP-LITE Flash Program Memory Fmcon Assembly language routine to erase/program all or part of a Accessing Additional Flash Elements UCFG1 ERASE-PROGRAMMING Additional Flash ElementsReading Additional Flash Elements Fmadrl Conf P89LPC906 User Configuration BytesUCFG1 SECx User Security BytesAddress xxxxh Unprogrammed value 00h Bootstat Bootvec Logical Arithmetic Data Transfer Mnemonic Description Bytes Cycles Hex Code Branching Boolean B8-BF RetiD8-DF Miscellaneous 2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908