Internal Reference Voltage, CIN1A CO1 CMP1 | Philips P89LPC907

Philips Semiconductors				User’s Manual - Preliminary -
ANALOG COMPARATORS				P89LPC906/907/908
	Comparator 1		OE1
			OE1
(P0.4) CIN1A	+
	+	CO1
		CO1		CMP1 (P0.6)
(P0.5) CMPREF				CMP1 (P0.6)
(P0.5) CMPREF	-
Vref	-		Change Detect
Vref			Change Detect
	CN1		CMF1	Interrupt
	CN1		CMF1
				EC

Figure 10-2: Comparator Input and Output Connections

CN1, OE1 = 0 0

CN1, OE1 = 0 1

CIN1A

+

CO1

CIN1A

+

CO1

CMP1

CMPREF

-

CMPREF

-

CN1, OE1 = 1 0

CN1, OE 1= 1 1

CIN1A

+

CO1

CIN1A

+

CO1

CMP1

Vref (1.23V)

-

Vref (1.23V)

-

Figure 10-3: Comparator Configurations

INTERNAL REFERENCE VOLTAGE

An internal reference voltage, Vref, may supply a default reference when a single comparator input pin is used. Please refer to the Datasheet for specifications.

COMPARATOR INTERRUPT

The comparator has an interrupt flag, CMF1, contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The interrupt will be generated when the interrupt enable bit EC in the IEN1 register is set and the interrupt system is enabled via the EA bit in the IEN0 register.

When a comparator is disabled the comparator’s output, COx, goes high. If the comparator output was low and then is disabled, the resulting transition of the comparator output from a low to high state will set the the comparator flag, CMFx. This will cause an interrupt if the comparator interrupt is enabled. The user should therefore disable the comparator interrupt prior to disabling the comparator. Additionally, the user should clear the comparator flag, CMFx, after disabling the comparator.

COMPARATOR AND POWER REDUCTION MODES

The comparator(s) may remain enabled when Power down or Idle mode is activated, but the comparator(s) are disabled automatically in Total Power down mode.

If the comparator interrupt is enabled (except in Total Power down mode), a change of the comparator output state will generate an interrupt and wake up the processor.

2003 Dec 8

74

Image 74

Philips P89LPC907 Internal Reference Voltage, Comparator Interrupt, Comparator and Power Reduction Modes, CIN1A CO1 CMP1

Contents

User Manual Table of Contents Brownout Detection Power-On Detection Power Reduction Modes Power-On reset code execution 103 List of Figures List of Figures PIN Configurations P89LPC906 Logic Symbols Product Comparison CPU Block Diagram P89LPC906KB Code Flash Oscillator Divider Byte Data RAM Block Diagram P89LPC907Uart Clock Block Diagram P89LPC908 Data RAM Port PIN Descriptions P89LPC906 TxD PIN Descriptions P89LPC907P1.0 P1.2 P1.1 PIN Descriptions P89LPC908Keyboard Input P1.0 P1.5 RxD Special function registers Special function registers table P89LPC906 MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 SFR Memory OrganizationData Code CPU Clock Oscclk Enhanced CPUClock Definitions LOW Speed Oscillator Option P89LPC906 ON-CHIP RC Oscillator Option Oscillator Option SELECTION- P89LPC906Clock Output P89LPC906 Watchdog Oscillator Option External Clock Input Option P89LPC906 CPU Clock Cclk Wakeup DelayBIT Symbol Function CPU Clock Cclk Modification Divm Register Med freq LOW Power Select P89LPC906High freq Low freq CPU Clocks Summary of Interrupts P89LPC906 Description Flag Bits Address Enable Bits Priority RankingInterrupt Priority Structure Interrupt Arbitration Summary of Interrupts P89LPC907,P89LPC908 Description External Interrupt InputsExternal Interrupt PIN Glitch Suppression TI & RI Bopd EBO Rtcf Kbif Interrupts Number of I/O Pins Available Clock Source Reset Option Port ConfigurationsQUASI-BIDIRECTIONAL Output Configuration RST Open Drain Output Configuration Port latch data Port 0 Analog Functions INPUT-ONLY ConfigurationPUSH-PULL Output Configuration Strong Port latch data Port pin Input data Glitch rejection Port Output Configuration P89LPC908 Port Output Configuration P89LPC906Port Output Configuration P89LPC907 Ports Ports TMOD.6 TmodTMOD.7 TMOD.3 Tamod P89LPC907 Overflows. ModeMode TAMOD.7-1 Tcon T0C/T = Overflow PclkT0C/T = Overflow TLn THn TFn Interrupt T0 Pin THn TFn TR0 ENT0 Pclk TH0 Timer Overflow Toggle Output P89LPC907Pclk TL0 Timers 0 REAL-TIME Clock Source Xclk FOSC2 FOSC1 FOSC0 RTCS10UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency Divm Cclk Undefined RC Oscillator/DIVMWDT Oscillator/DIVM External clock/DIVM REAL-TIME Clock INTERRUPT/WAKE UP Reset Sources Affecting the REAL-TIME ClockChanging RTCS1-0 Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Brownout Options POWER-ON DetectionPower Reduction Modes Power Reduction Modes Pcon Pcona Power Monitoring Functions Uart Modes Updating the BRGR1 and BRGR0 Sfrs SFR SpaceBaud Rate Generator and Selection SFR Locations for UARTs Brgcon Framing ErrorBreak Detect Scon More about Uart Mode Sstat Serial Port Mode 0 Double Buffering Must Be Disabled More about Uart Modes 2 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 PCON.6 RB8 SMOD0 Double Buffering Double Buffering in Different Modes 9TH BIT BIT 8 in Double Buffering Modes 1, 2 Transmission with and without Double Buffering Multiprocessor Communications Automatic Address Recognition Uart Uart POWER-ON Reset Code Execution Block Diagram of Reset Rstsrc Comparator Configuration Comparator Interrupt Comparator and Power Reduction ModesInternal Reference Voltage CIN1A CO1 CMP1 Cmpref Comparator Configuration Example Analog Comparators Kbpatn Kbcon Kbmask Wdte Wdse Function Watchdog timer configurationWatchdog Function Feed Sequence Wdcon P89LPC906/907/908 Watchdog Timeout Values PRE2-PRE0 Watchdog Watchdog Timer in Timer ModePrescaler Reset Pclk Control register Prescaler Power Down OperationWatchdog Clock Source CLK Watchdog Timer Watchdog Timer AUXR1 Software ResetDual Data Pointers MOVXA, @DPTR MOVCA, @A+DPTRMove code byte relative to Dptr to the accumulator MOVX@DPTR, a General Description FeaturesUsing Flash AS Data Storage Introduction to IAP-LITE Flash Program Memory Fmcon Accessing Additional Flash Elements Assembly language routine to erase/program all or part of a UCFG1 ERASE-PROGRAMMING Additional Flash ElementsReading Additional Flash Elements Fmadrl Conf P89LPC906 User Configuration BytesUCFG1 Address xxxxh User Security BytesSECx Unprogrammed value 00h Bootvec Bootstat Arithmetic Logical Mnemonic Description Bytes Cycles Hex Code Data Transfer Boolean Branching D8-DF RetiB8-BF Miscellaneous 2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908