Ports | Philips P89LPC906, P89LPC908, P89LPC907 guide

Philips Semiconductors	User’s Manual - Preliminary -

I/O PORTS	P89LPC906/907/908

All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.

2003 Dec 8

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Philips P89LPC906, P89LPC908, P89LPC907 user manual Ports

Contents

User Manual Table of Contents Power-On reset code execution Brownout Detection Power-On Detection Power Reduction Modes 103 List of Figures List of Figures P89LPC906 PIN Configurations Product Comparison Logic Symbols Oscillator Divider Block Diagram P89LPC906KB Code Flash CPU Clock Block Diagram P89LPC907Uart Byte Data RAM Data RAM Port Block Diagram P89LPC908 PIN Descriptions P89LPC906 P1.2 PIN Descriptions P89LPC907P1.0 TxD RxD PIN Descriptions P89LPC908Keyboard Input P1.0 P1.5 P1.1 Special function registers table P89LPC906 Special function registers MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Code Memory OrganizationData SFR LOW Speed Oscillator Option P89LPC906 Enhanced CPUClock Definitions CPU Clock Oscclk Watchdog Oscillator Option Oscillator Option SELECTION- P89LPC906Clock Output P89LPC906 ON-CHIP RC Oscillator Option CPU Clock Cclk Modification Divm Register CPU Clock Cclk Wakeup DelayBIT Symbol Function External Clock Input Option P89LPC906 Low freq LOW Power Select P89LPC906High freq Med freq CPU Clocks Interrupt Arbitration Flag Bits Address Enable Bits Priority RankingInterrupt Priority Structure Summary of Interrupts P89LPC906 Description TI & RI External Interrupt InputsExternal Interrupt PIN Glitch Suppression Summary of Interrupts P89LPC907,P89LPC908 Description Bopd EBO Rtcf Kbif Interrupts RST Port ConfigurationsQUASI-BIDIRECTIONAL Output Configuration Number of I/O Pins Available Clock Source Reset Option Port latch data Open Drain Output Configuration Strong Port latch data Port pin Input data Glitch rejection INPUT-ONLY ConfigurationPUSH-PULL Output Configuration Port 0 Analog Functions Port Output Configuration P89LPC906 Port Output Configuration P89LPC907Port Output Configuration P89LPC908 Ports Ports TMOD.3 TmodTMOD.7 TMOD.6 TAMOD.7-1 Overflows. ModeMode Tamod P89LPC907 Tcon THn TFn PclkT0C/T = Overflow TLn THn TFn Interrupt T0 Pin T0C/T = Overflow Timer Overflow Toggle Output P89LPC907 Pclk TL0TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source Divm Cclk FOSC2 FOSC1 FOSC0 RTCS10UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency Xclk External clock/DIVM RC Oscillator/DIVMWDT Oscillator/DIVM Undefined Reset Sources Affecting the REAL-TIME Clock Changing RTCS1-0REAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection POWER-ON Detection Power Reduction ModesBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Modes Uart SFR Locations for UARTs SFR SpaceBaud Rate Generator and Selection Updating the BRGR1 and BRGR0 Sfrs Framing Error Break DetectBrgcon Scon Sstat More about Uart Mode Serial Port Mode 0 Double Buffering Must Be Disabled PCON.6 RB8 SMOD0 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 More about Uart Modes 2 Double Buffering in Different Modes Double Buffering Transmission with and without Double Buffering 9TH BIT BIT 8 in Double Buffering Modes 1, 2 Automatic Address Recognition Multiprocessor Communications Uart Uart Block Diagram of Reset POWER-ON Reset Code Execution Rstsrc Comparator Configuration CIN1A CO1 CMP1 Cmpref Comparator and Power Reduction ModesInternal Reference Voltage Comparator Interrupt Comparator Configuration Example Analog Comparators Kbcon Kbpatn Kbmask Watchdog timer configuration Watchdog FunctionWdte Wdse Function Feed Sequence Wdcon PRE2-PRE0 P89LPC906/907/908 Watchdog Timeout Values Control register Watchdog Timer in Timer ModePrescaler Reset Pclk Watchdog CLK Power Down OperationWatchdog Clock Source Prescaler Watchdog Timer Watchdog Timer Software Reset Dual Data PointersAUXR1 MOVX@DPTR, a MOVCA, @A+DPTRMove code byte relative to Dptr to the accumulator MOVXA, @DPTR Introduction to IAP-LITE FeaturesUsing Flash AS Data Storage General Description Flash Program Memory Fmcon Assembly language routine to erase/program all or part of a Accessing Additional Flash Elements ERASE-PROGRAMMING Additional Flash Elements Reading Additional Flash ElementsUCFG1 Fmadrl Conf User Configuration Bytes UCFG1P89LPC906 Unprogrammed value 00h User Security BytesSECx Address xxxxh Bootstat Bootvec Logical Arithmetic Data Transfer Mnemonic Description Bytes Cycles Hex Code Branching Boolean Miscellaneous RetiB8-BF D8-DF 2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908