Philips Semiconductors |
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| User’s Manual - Preliminary - | ||
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GENERAL DESCRIPTION | P89LPC906/907/908 | |||||
PIN DESCRIPTIONS - P89LPC906 |
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Mnemonic | Pin no. | Type | Name and function |
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P0.4 - P0.6 | 3, 7,8 | I/O | Port 0: | Port 0 is an I/O port with a | ||
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| 0 latches are configured in the input only mode with the internal pullup | ||
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| disabled. The operation of port 0 pins as inputs and outputs depends upon | ||
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| the port configuration selected. Each port pin is configured independently. | ||
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| Refer to the section Port Configurations on page 35 and the DC Electrical | ||
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| Characteristics in the datasheet for details. |
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| The Keypad Interrupt feature operates with port 0 pins. |
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| All pins have Schmitt triggered inputs. |
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| Port 0 also provides various special functions as described below. | |||
| 8 | I/O | P0.4 | Port 0 bit 4. |
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| I | CIN1A | Comparator 1 positive input. |
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| I | KBI4 | Keyboard Input 4. |
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| 7 | I/O | P0.5 | Port 0 bit 5. |
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| I | CMPREFComparator reference (negative) input. |
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| I | KBI5 | Keyboard Input 5. |
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| 3 | I/O | P0.6 | Port 0 bit 6. |
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| O | CMP1 | Comparator 1 output. |
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| I | KBI6 | Keyboard Input 6. |
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P1.5 | 1 | I | P1.5 | Port 1 bit 5. (Input only) |
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| I | RST | External Reset input during | ||
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| functioning as a reset input a low on this pin resets the microcontroller, | ||
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| causing I/O ports and peripherals to take on their default states, and the | ||
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| processor begins execution at address 0. Also used during a | ||
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| sequence to force | ||
P3.0 - P3.1 | 4,5 | I/O | Port 3 | Port 3 is an I/O port with a | ||
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| 3 latches are configured in the input only mode with the internal pullups | ||
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| disabled. The operation of port 3 pins as inputs and outputs depends upon | ||
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| the port configuration selected. Each port pin is configured independently. | ||
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| Refer to the section Port Configurations on page 35 and the DC Electrical | ||
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| Characteristics in the datasheet for details. |
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| All pins have Schmitt triggered inputs. |
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| Port 3 also provides various special functions as described below: | |||
| 5 | I/O | P3.0 | Port 3 bit 0. |
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| O | XTAL2 Output from the oscillator amplifier (when a crystal oscillator option is | |||
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| selected via the FLASH configuration). |
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| O | CLKOUTCPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It can | |||
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| be used if the CPU clock is the internal RC oscillator, watchdog oscillator or | ||
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| external clock input, except when XTAL1/XTAL2 are used to generate clock | ||
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| source for the |
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| 4 | I/O | P3.1 | Port 3 bit 1. |
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| I | XTAL1 | Input to the oscillator circuit and internal clock generator circuits (when | ||
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| selected via the FLASH configuration). It can be a port pin if internal RC | ||
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| oscillator or watchdog oscillator is used as the CPU clock source, AND if | ||
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| XTAL1/XTAL2 are not used to generate the clock for the | ||
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| system timer. |
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VSS | 2 | I | Ground: 0V reference. |
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VDD | 6 | I | Power Supply: This is the power supply voltage for normal operation as well as Idle and | |||
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| Power down modes. |
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2003 Dec 8 | 12 |