P89LPC906/907/908 Watchdog Timeout Values | Philips P89LPC908

	Philips Semiconductors				User’s Manual - Preliminary -

	WATCHDOG TIMER				P89LPC906/907/908
	Table 12-2: P89LPC906/907/908 Watchdog Timeout Values
			Timeout Period	Watchdog Clock Source
			Timeout Period
	PRE2-PRE0	WDL in decimal)	(in watchdog clock
	PRE2-PRE0	WDL in decimal)	(in watchdog clock	400KHz Watchdog Oscillator Clock	12MHz CCLK (6MHz CCLK/2
			cycles)	400KHz Watchdog Oscillator Clock	12MHz CCLK (6MHz CCLK/2
			cycles)	(Nominal)	Watchdog Clock)
				(Nominal)	Watchdog Clock)

	000	0	33	82.5µs	5.50µs

		255	8,193	20.5ms	1.37ms
		255	8,193	20.5ms	1.37ms

	001	0	65	162.5µs	10.8µs

		255	16,385	41.0ms	2.73ms
		255	16,385	41.0ms	2.73ms

	010	0	129	322.5µs	21.5µs

		255	32,769	81.9ms	5.46ms
		255	32,769	81.9ms	5.46ms

	011	0	257	642.5µs	42.8µs

		255	65,537	163.8ms	10.9ms
		255	65,537	163.8ms	10.9ms

	100	0	513	.1.28ms	85.5µs

		255	131,073	327.7ms	21.8ms
		255	131,073	327.7ms	21.8ms

	101	0	1,025	2.56ms	170.8µs

		255	262,145	655.4ms	43.7ms
		255	262,145	655.4ms	43.7ms

	110	0	2,049	5.12ms	341.5µs

		255	524,289	1.31s	87.4ms
		255	524,289	1.31s	87.4ms

	111	0	4097	10.2ms	682.8µs

		255	1,048,577	2.62s	174.8ms
		255	1,048,577	2.62s	174.8ms

2003 Dec 8

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Philips P89LPC908, P89LPC907 user manual P89LPC906/907/908 Watchdog Timeout Values, PRE2-PRE0

Contents

User Manual Table of Contents Brownout Detection Power-On Detection Power Reduction Modes Power-On reset code execution 103 List of Figures List of Figures PIN Configurations P89LPC906 Logic Symbols Product Comparison CPU Block Diagram P89LPC906KB Code Flash Oscillator Divider Byte Data RAM Block Diagram P89LPC907Uart Clock Block Diagram P89LPC908 Data RAM Port PIN Descriptions P89LPC906 TxD PIN Descriptions P89LPC907P1.0 P1.2 P1.1 PIN Descriptions P89LPC908Keyboard Input P1.0 P1.5 RxD Special function registers Special function registers table P89LPC906 MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 SFR Memory OrganizationData Code CPU Clock Oscclk Enhanced CPUClock Definitions LOW Speed Oscillator Option P89LPC906 ON-CHIP RC Oscillator Option Oscillator Option SELECTION- P89LPC906Clock Output P89LPC906 Watchdog Oscillator Option External Clock Input Option P89LPC906 CPU Clock Cclk Wakeup DelayBIT Symbol Function CPU Clock Cclk Modification Divm Register Med freq LOW Power Select P89LPC906High freq Low freq CPU Clocks Summary of Interrupts P89LPC906 Description Flag Bits Address Enable Bits Priority RankingInterrupt Priority Structure Interrupt Arbitration Summary of Interrupts P89LPC907,P89LPC908 Description External Interrupt InputsExternal Interrupt PIN Glitch Suppression TI & RI Bopd EBO Rtcf Kbif Interrupts Number of I/O Pins Available Clock Source Reset Option Port ConfigurationsQUASI-BIDIRECTIONAL Output Configuration RST Open Drain Output Configuration Port latch data Port 0 Analog Functions INPUT-ONLY ConfigurationPUSH-PULL Output Configuration Strong Port latch data Port pin Input data Glitch rejection Port Output Configuration P89LPC907 Port Output Configuration P89LPC906Port Output Configuration P89LPC908 Ports Ports TMOD.6 TmodTMOD.7 TMOD.3 Tamod P89LPC907 Overflows. ModeMode TAMOD.7-1 Tcon T0C/T = Overflow PclkT0C/T = Overflow TLn THn TFn Interrupt T0 Pin THn TFn Pclk TL0 Timer Overflow Toggle Output P89LPC907TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source Xclk FOSC2 FOSC1 FOSC0 RTCS10UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency Divm Cclk Undefined RC Oscillator/DIVMWDT Oscillator/DIVM External clock/DIVM Changing RTCS1-0 Reset Sources Affecting the REAL-TIME ClockREAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Power Reduction Modes POWER-ON DetectionBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Uart Modes Updating the BRGR1 and BRGR0 Sfrs SFR SpaceBaud Rate Generator and Selection SFR Locations for UARTs Break Detect Framing ErrorBrgcon Scon More about Uart Mode Sstat Serial Port Mode 0 Double Buffering Must Be Disabled More about Uart Modes 2 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 PCON.6 RB8 SMOD0 Double Buffering Double Buffering in Different Modes 9TH BIT BIT 8 in Double Buffering Modes 1, 2 Transmission with and without Double Buffering Multiprocessor Communications Automatic Address Recognition Uart Uart POWER-ON Reset Code Execution Block Diagram of Reset Rstsrc Comparator Configuration Comparator Interrupt Comparator and Power Reduction ModesInternal Reference Voltage CIN1A CO1 CMP1 Cmpref Comparator Configuration Example Analog Comparators Kbpatn Kbcon Kbmask Watchdog Function Watchdog timer configurationWdte Wdse Function Feed Sequence Wdcon P89LPC906/907/908 Watchdog Timeout Values PRE2-PRE0 Watchdog Watchdog Timer in Timer ModePrescaler Reset Pclk Control register Prescaler Power Down OperationWatchdog Clock Source CLK Watchdog Timer Watchdog Timer Dual Data Pointers Software ResetAUXR1 MOVXA, @DPTR MOVCA, @A+DPTRMove code byte relative to Dptr to the accumulator MOVX@DPTR, a General Description FeaturesUsing Flash AS Data Storage Introduction to IAP-LITE Flash Program Memory Fmcon Accessing Additional Flash Elements Assembly language routine to erase/program all or part of a Reading Additional Flash Elements ERASE-PROGRAMMING Additional Flash ElementsUCFG1 Fmadrl Conf UCFG1 User Configuration BytesP89LPC906 Address xxxxh User Security BytesSECx Unprogrammed value 00h Bootvec Bootstat Arithmetic Logical Mnemonic Description Bytes Cycles Hex Code Data Transfer Boolean Branching D8-DF RetiB8-BF Miscellaneous 2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908