CMP1 Cmpref | Philips P89LPC908, P89LPC906, P89LPC907 guide

Philips Semiconductors

User’s Manual - Preliminary -

GENERAL DESCRIPTION

P89LPC906/907/908

Name

Description

SFR

Bit Functions and Addresses

Reset Value

Address

MSB

LSB

Hex

Binary

KBMASK#

Keypad Interrupt Mask Register

86H

00H

00000000

KBPATN#

Keypad Pattern Register

93H

FFH

11111111

87

86

85

84

83

82

81

80

P0*

Port 0

80H

-

CMP1/

CMPREF/

CIN1A/

-

KB2

-

KB0

Note 1

KB6

KB5

KB4

97

96

95

94

93

92

91

90

P1*

Port 1

90H

-

-

-

-

T0

-

TxD

RST

B7

B6

B5

B4

B3

B2

B1

B0

P0M1#

Port 0 Output Mode 1

84H

-

(P0M1.6)

(P0M1.5)

(P0M1.4)

-

(P0M1.2)

-

(P0M1.0)

FFH

11111111

P0M2#

Port 0 Output Mode 2

85H

-

(P0M2.6)

(P0M2.5)

(P0M2.4)

-

(P0M2.2)

-

(P0M2.0)

00H

00000000

FFH1

11111111

P1M1#

Port 1 Output Mode 1

91H

-

-

(P1M1.5)

-

-

(P1M1.2)

-

(P1M1.0)

P1M2#

Port 1 Output Mode 2

92H

-

-

(P1M2.5)

-

-

(P1M2.2)

-

(P1M2.0)

00H1

00000000

PCON#

Power Control Register

87H

SMOD1

SMOD0

BOPD

BOI

GF1

GF0

PMOD1

PMOD0

00H

00000000

00H1

00000000

PCONA#

Power Control Register A

B5H

RTCPD

VCPD

-

SPD

D7

D6

D5

D4

D3

D2

D1

D0

PSW*

Program Status Word

D0H

CY

AC

F0

RS1

RS0

OV

F1

P

00H

00000000

PT0AD#

Port 0 Digital Input Disable

F6H

-

-

PT0AD.5

PT0AD.4

-

-

-

-

00H

xx00000x

RSTSRC#

Reset Source Register

DFH

-

-

BOF

POF

-

R_WD

R_SF

R_EX

Note 2

60H1,5

011xxx00

RTCCON#

Real-Time Clock Control

D1H

RTCF

RTCS1

RTCS0

-

-

-

ERTC

RTCEN

RTCH#

Real-Time Clock Register High

D2H

00H5

00000000

RTCL#

Real-Time Clock Register Low

D3H

00H5

00000000

SBUF

Serial Port Data Buffer Register

99H

xxH

xxxxxxxx

9F

9E

9D

9C

9B

9A

99

98

SCON*

Serial Port Control

98H

SM0

SM1

SM2

-

TB8

-

TI

-

00H

00000000

SSTAT#

Serial Port Extended Status Register

BAH

DBMOD

INTLO

CIDIS

DBISEL

-

-

-

-

00H

00000000

SP

Stack Pointer

81H

07H

00000111

TAMOD#

Timer 0 Auxiliary Mode

8FH

-

-

-

-

-

-

-

T0M2

00H

xxx0xxx0

8F

8E

8D

8C

8B

8A

89

88

TCON*

Timer 0 and 1 Control

88H

TF1

TR1

TF0

TR0

-

-

-

-

00H

00000000

2003 Dec 8

19

Image 19

Philips P89LPC908, P89LPC906, P89LPC907 user manual CMP1 Cmpref

Contents

User Manual Table of Contents Power-On reset code execution Brownout Detection Power-On Detection Power Reduction Modes 103 List of Figures List of Figures P89LPC906 PIN Configurations Product Comparison Logic Symbols Oscillator Divider Block Diagram P89LPC906KB Code Flash CPU Clock Block Diagram P89LPC907Uart Byte Data RAM Data RAM Port Block Diagram P89LPC908 PIN Descriptions P89LPC906 P1.2 PIN Descriptions P89LPC907P1.0 TxD RxD PIN Descriptions P89LPC908Keyboard Input P1.0 P1.5 P1.1 Special function registers table P89LPC906 Special function registers MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Code Memory OrganizationData SFR LOW Speed Oscillator Option P89LPC906 Enhanced CPUClock Definitions CPU Clock Oscclk Watchdog Oscillator Option Oscillator Option SELECTION- P89LPC906Clock Output P89LPC906 ON-CHIP RC Oscillator Option CPU Clock Cclk Modification Divm Register CPU Clock Cclk Wakeup DelayBIT Symbol Function External Clock Input Option P89LPC906 Low freq LOW Power Select P89LPC906High freq Med freq CPU Clocks Interrupt Arbitration Flag Bits Address Enable Bits Priority RankingInterrupt Priority Structure Summary of Interrupts P89LPC906 Description TI & RI External Interrupt InputsExternal Interrupt PIN Glitch Suppression Summary of Interrupts P89LPC907,P89LPC908 Description Bopd EBO Rtcf Kbif Interrupts RST Port ConfigurationsQUASI-BIDIRECTIONAL Output Configuration Number of I/O Pins Available Clock Source Reset Option Port latch data Open Drain Output Configuration Strong Port latch data Port pin Input data Glitch rejection INPUT-ONLY ConfigurationPUSH-PULL Output Configuration Port 0 Analog Functions Port Output Configuration P89LPC907 Port Output Configuration P89LPC906Port Output Configuration P89LPC908 Ports Ports TMOD.3 TmodTMOD.7 TMOD.6 TAMOD.7-1 Overflows. ModeMode Tamod P89LPC907 Tcon THn TFn PclkT0C/T = Overflow TLn THn TFn Interrupt T0 Pin T0C/T = Overflow Pclk TL0 Timer Overflow Toggle Output P89LPC907TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source Divm Cclk FOSC2 FOSC1 FOSC0 RTCS10UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency Xclk External clock/DIVM RC Oscillator/DIVMWDT Oscillator/DIVM Undefined Changing RTCS1-0 Reset Sources Affecting the REAL-TIME ClockREAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Power Reduction Modes POWER-ON DetectionBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Modes Uart SFR Locations for UARTs SFR SpaceBaud Rate Generator and Selection Updating the BRGR1 and BRGR0 Sfrs Break Detect Framing ErrorBrgcon Scon Sstat More about Uart Mode Serial Port Mode 0 Double Buffering Must Be Disabled PCON.6 RB8 SMOD0 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 More about Uart Modes 2 Double Buffering in Different Modes Double Buffering Transmission with and without Double Buffering 9TH BIT BIT 8 in Double Buffering Modes 1, 2 Automatic Address Recognition Multiprocessor Communications Uart Uart Block Diagram of Reset POWER-ON Reset Code Execution Rstsrc Comparator Configuration CIN1A CO1 CMP1 Cmpref Comparator and Power Reduction ModesInternal Reference Voltage Comparator Interrupt Comparator Configuration Example Analog Comparators Kbcon Kbpatn Kbmask Watchdog Function Watchdog timer configurationWdte Wdse Function Feed Sequence Wdcon PRE2-PRE0 P89LPC906/907/908 Watchdog Timeout Values Control register Watchdog Timer in Timer ModePrescaler Reset Pclk Watchdog CLK Power Down OperationWatchdog Clock Source Prescaler Watchdog Timer Watchdog Timer Dual Data Pointers Software ResetAUXR1 MOVX@DPTR, a MOVCA, @A+DPTRMove code byte relative to Dptr to the accumulator MOVXA, @DPTR Introduction to IAP-LITE FeaturesUsing Flash AS Data Storage General Description Flash Program Memory Fmcon Assembly language routine to erase/program all or part of a Accessing Additional Flash Elements Reading Additional Flash Elements ERASE-PROGRAMMING Additional Flash ElementsUCFG1 Fmadrl Conf UCFG1 User Configuration BytesP89LPC906 Unprogrammed value 00h User Security BytesSECx Address xxxxh Bootstat Bootvec Logical Arithmetic Data Transfer Mnemonic Description Bytes Cycles Hex Code Branching Boolean Miscellaneous RetiB8-BF D8-DF 2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908