User Configuration Bytes, UCFG1 | Philips P89LPC906, P89LPC908

Philips Semiconductors	User’s Manual - Preliminary -

FLASH PROGRAM MEMORY	P89LPC906/907/908
USER CONFIGURATION BYTES

A number of user-configurable features of the P89LPC906/907/908 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of Flash byte UCFG1 shown in Figure 14-7.

UCFG1

Address: xxxxh

Default: 63h

7	6	5	4	3	2	1	0
WDTE	RPE	BOE	WDSE	-	FOSC2	FOSC1	FOSC0

BIT	SYMBOL			FUNCTION
UCFG1.7	WDTE			Watchdog timer reset enable. When set =1, enables the watchdog timer reset. When
				cleared = 0, dusables the watchdog timer reset.The timer may still be used to generate an
				interrupt. Refer to Table 13-1for details.
UCFG1.6	RPE			Reset pin enable. When set =1, enables the reset function of pin P1.5. When cleared, P1.5
				may be used as an input pin. NOTE: During a power-up sequence, the RPE selection is
				overriden and this pin will always functions as a reset input. After power-up the pin will
				function as defined by the RPE bit. Only a power-up reset will temporarily override the
				selection defined by RPE bit. Other sources of reset will not override the RPE bit.
UCFG1.5	BOE			Brownout Detect Enable (see section "Brownout Detection" on page 53).
UCFG1.4	WDSE			Watchdog Safety Enable bit. Refer to Table for details.
UCFG1.3		-		Reserved (should remain unprogrammed at zero).
UCFG1.2-0	FOSC2-FSOC0			CPU oscillator type select. See section "Low Power Select (P89LPC906)" on page 28 for
				additional information. Combinations other than those shown below should not be used.
				They are reserved for future use.When FOSC2:0 select either the internal RC or
				Watchdog oscillators, the crystal oscillator configuration is controlled by RTCCON. See
				Table and Table . Note: External clock input and crystal options are available on the
				P89LPC906.
	FOSC2-FOSC0			Oscillator Configuration
	1	1	1	External clock input on XTAL1.
	1	0	0	Watchdog Oscillator, 400KHz (+20/ -30% tolerance).
	0	1	1	Internal RC oscillator, 7.373MHz ±2.5%.
	0	1	0	Low frequency crystal, 20 kHz to 100 kHz.
	0	0	1	Medium frequency crystal or resonator, 100 kHz to 4 MHz.
	0	0	0	High frequency crystal or resonator, 4 MHz to 12 MHz.

Factory default value for UCFG1 is set for watchdog reset disabled, reset pin enabled, brownout detect enabled, and using the internal RC oscillator

Figure 14-7: Flash User Configuration Byte 1 (UCFG1)

2003 Dec 8

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Image 96

Philips P89LPC906, P89LPC908, P89LPC907 user manual User Configuration Bytes, UCFG1

Contents

User Manual Table of Contents Brownout Detection Power-On Detection Power Reduction Modes Power-On reset code execution 103 List of Figures List of Figures PIN Configurations P89LPC906 Logic Symbols Product Comparison Block Diagram P89LPC906 KB Code FlashCPU Oscillator Divider Block Diagram P89LPC907 UartByte Data RAM Clock Block Diagram P89LPC908 Data RAM Port PIN Descriptions P89LPC906 PIN Descriptions P89LPC907 P1.0TxD P1.2 PIN Descriptions P89LPC908 Keyboard Input P1.0 P1.5P1.1 RxD Special function registers Special function registers table P89LPC906 MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Memory Organization DataSFR Code Enhanced CPU Clock DefinitionsCPU Clock Oscclk LOW Speed Oscillator Option P89LPC906 Oscillator Option SELECTION- P89LPC906 Clock Output P89LPC906ON-CHIP RC Oscillator Option Watchdog Oscillator Option CPU Clock Cclk Wakeup Delay BIT Symbol FunctionExternal Clock Input Option P89LPC906 CPU Clock Cclk Modification Divm Register LOW Power Select P89LPC906 High freqMed freq Low freq CPU Clocks Flag Bits Address Enable Bits Priority Ranking Interrupt Priority StructureSummary of Interrupts P89LPC906 Description Interrupt Arbitration External Interrupt Inputs External Interrupt PIN Glitch SuppressionSummary of Interrupts P89LPC907,P89LPC908 Description TI & RI Bopd EBO Rtcf Kbif Interrupts Port Configurations QUASI-BIDIRECTIONAL Output ConfigurationNumber of I/O Pins Available Clock Source Reset Option RST Open Drain Output Configuration Port latch data INPUT-ONLY Configuration PUSH-PULL Output ConfigurationPort 0 Analog Functions Strong Port latch data Port pin Input data Glitch rejection Port Output Configuration P89LPC906 Port Output Configuration P89LPC907Port Output Configuration P89LPC908 Ports Ports Tmod TMOD.7TMOD.6 TMOD.3 Overflows. Mode ModeTamod P89LPC907 TAMOD.7-1 Tcon Pclk T0C/T = Overflow TLn THn TFn Interrupt T0 PinT0C/T = Overflow THn TFn Timer Overflow Toggle Output P89LPC907 Pclk TL0TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source FOSC2 FOSC1 FOSC0 RTCS10 UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock FrequencyXclk Divm Cclk RC Oscillator/DIVM WDT Oscillator/DIVMUndefined External clock/DIVM Reset Sources Affecting the REAL-TIME Clock Changing RTCS1-0REAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection POWER-ON Detection Power Reduction ModesBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Uart Modes SFR Space Baud Rate Generator and SelectionUpdating the BRGR1 and BRGR0 Sfrs SFR Locations for UARTs Framing Error Break DetectBrgcon Scon More about Uart Mode Sstat Serial Port Mode 0 Double Buffering Must Be Disabled Framing Error and RI in Modes 2 and 3 with SM2 = FE and RI when SM2 = 1 in Modes 2More about Uart Modes 2 PCON.6 RB8 SMOD0 Double Buffering Double Buffering in Different Modes 9TH BIT BIT 8 in Double Buffering Modes 1, 2 Transmission with and without Double Buffering Multiprocessor Communications Automatic Address Recognition Uart Uart POWER-ON Reset Code Execution Block Diagram of Reset Rstsrc Comparator Configuration Comparator and Power Reduction Modes Internal Reference VoltageComparator Interrupt CIN1A CO1 CMP1 Cmpref Comparator Configuration Example Analog Comparators Kbpatn Kbcon Kbmask Watchdog timer configuration Watchdog FunctionWdte Wdse Function Feed Sequence Wdcon P89LPC906/907/908 Watchdog Timeout Values PRE2-PRE0 Watchdog Timer in Timer Mode Prescaler Reset PclkWatchdog Control register Power Down Operation Watchdog Clock SourcePrescaler CLK Watchdog Timer Watchdog Timer Software Reset Dual Data PointersAUXR1 MOVCA, @A+DPTR Move code byte relative to Dptr to the accumulatorMOVXA, @DPTR MOVX@DPTR, a Features Using Flash AS Data StorageGeneral Description Introduction to IAP-LITE Flash Program Memory Fmcon Accessing Additional Flash Elements Assembly language routine to erase/program all or part of a ERASE-PROGRAMMING Additional Flash Elements Reading Additional Flash ElementsUCFG1 Fmadrl Conf User Configuration Bytes UCFG1P89LPC906 User Security Bytes SECxAddress xxxxh Unprogrammed value 00h Bootvec Bootstat Arithmetic Logical Mnemonic Description Bytes Cycles Hex Code Data Transfer Boolean Branching Reti B8-BFD8-DF Miscellaneous 2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908