KB2 KB6 KB5 KB4 | Philips P89LPC908, P89LPC906, P89LPC907 specification

Philips Semiconductors

User’s Manual - Preliminary -

GENERAL DESCRIPTION

P89LPC906/907/908

Name

Description

SFR

Bit Functions and Addresses

Reset Value

Address

MSB

LSB

Hex

Binary

KBMASK#

Keypad Interrupt Mask Register

86H

00H

00000000

KBPATN#

Keypad Pattern Register

93H

FFH

11111111

87

86

85

84

83

82

81

80

P0*

Port 0

80H

-

CMP1/

CMPREF/

CIN1A/

-

KB2

-

-

Note 1

KB6

KB5

KB4

97

96

95

94

93

92

91

90

P1*

Port 1

90H

-

-

-

-

-

RxD

TxD

RST

P0M1#

Port 0 Output Mode 1

84H

-

(P0M1.6)

(P0M1.5)

(P0M1.4)

-

(P0M1.2)

-

-

FFH

11111111

P0M2#

Port 0 Output Mode 2

85H

-

(P0M2.6)

(P0M2.5)

(P0M2.4)

-

(P0M2.2)

-

-

00H

00000000

FFH1

11111111

P1M1#

Port 1 Output Mode 1

91H

-

-

(P1M1.5)

-

-

-

(P1M1.1)

(P1M1.0)

P1M2#

Port 1 Output Mode 2

92H

-

-

(P1M2.5)

-

-

-

(P1M2.1)

(P1M2.0)

00H1

00000000

PCON#

Power Control Register

87H

SMOD1

SMOD0

BOPD

BOI

GF1

GF0

PMOD1

PMOD0

00H

00000000

00H1

00000000

PCONA#

Power Control Register A

B5H

RTCPD

VCPD

-

SPD

D7

D6

D5

D4

D3

D2

D1

D0

PSW*

Program Status Word

D0H

CY

AC

F0

RS1

RS0

OV

F1

P

00H

00000000

PT0AD#

Port 0 Digital Input Disable

F6H

-

-

PT0AD.5

PT0AD.4

-

PT0AD.2

-

-

00H

xx00000x

RSTSRC#

Reset Source Register

DFH

-

-

BOF

POF

R_BK

R_WD

R_SF

R_EX

Note 2

60H1,5

011xxx00

RTCCON#

Real-Time Clock Control

D1H

RTCF

RTCS1

RTCS0

-

-

-

ERTC

RTCEN

RTCH#

Real-Time Clock Register High

D2H

00H5

00000000

RTCL#

Real-Time Clock Register Low

D3H

00H5

00000000

SADDR#

Serial Port Address Register

A9H

00H

00000000

SADEN#

Serial Port Address Enable

B9H

00H

00000000

SBUF

Serial Port Data Buffer Register

99H

xxH

xxxxxxxx

9F

9E

9D

9C

9B

9A

99

98

SCON*

Serial Port Control

98H

SM0/FE

SM1

SM2

REN

TB8

RB8

TI

RI

00H

00000000

SSTAT#

Serial Port Extended Status Register

BAH

DBMOD

INTLO

CIDIS

DBISEL

FE

BR

OE

STINT

00H

00000000

SP

Stack Pointer

81H

07H

00000111

8F

8E

8D

8C

8B

8A

89

88

TCON*

Timer 0 and 1 Control

88H

TF1

TR1

TF0

TR0

-

-

-

-

00H

00000000

TH0

Timer 0 High

8CH

00H

00000000

TH1

Timer 1 High

8DH

00H

00000000

2003 Dec 8

22

Image 22

Philips P89LPC908, P89LPC906, P89LPC907 user manual KB2 KB6 KB5 KB4

Contents

User Manual Table of Contents Brownout Detection Power-On Detection Power Reduction Modes Power-On reset code execution 103 List of Figures List of Figures PIN Configurations P89LPC906 Logic Symbols Product Comparison CPU Block Diagram P89LPC906KB Code Flash Oscillator Divider Byte Data RAM Block Diagram P89LPC907Uart Clock Block Diagram P89LPC908 Data RAM Port PIN Descriptions P89LPC906 TxD PIN Descriptions P89LPC907P1.0 P1.2 P1.1 PIN Descriptions P89LPC908Keyboard Input P1.0 P1.5 RxD Special function registers Special function registers table P89LPC906 MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 SFR Memory OrganizationData Code CPU Clock Oscclk Enhanced CPUClock Definitions LOW Speed Oscillator Option P89LPC906 ON-CHIP RC Oscillator Option Oscillator Option SELECTION- P89LPC906Clock Output P89LPC906 Watchdog Oscillator Option External Clock Input Option P89LPC906 CPU Clock Cclk Wakeup DelayBIT Symbol Function CPU Clock Cclk Modification Divm Register Med freq LOW Power Select P89LPC906High freq Low freq CPU Clocks Summary of Interrupts P89LPC906 Description Flag Bits Address Enable Bits Priority RankingInterrupt Priority Structure Interrupt Arbitration Summary of Interrupts P89LPC907,P89LPC908 Description External Interrupt InputsExternal Interrupt PIN Glitch Suppression TI & RI Bopd EBO Rtcf Kbif Interrupts Number of I/O Pins Available Clock Source Reset Option Port ConfigurationsQUASI-BIDIRECTIONAL Output Configuration RST Open Drain Output Configuration Port latch data Port 0 Analog Functions INPUT-ONLY ConfigurationPUSH-PULL Output Configuration Strong Port latch data Port pin Input data Glitch rejection Port Output Configuration P89LPC907 Port Output Configuration P89LPC906Port Output Configuration P89LPC908 Ports Ports TMOD.6 TmodTMOD.7 TMOD.3 Tamod P89LPC907 Overflows. ModeMode TAMOD.7-1 Tcon T0C/T = Overflow PclkT0C/T = Overflow TLn THn TFn Interrupt T0 Pin THn TFn Pclk TL0 Timer Overflow Toggle Output P89LPC907TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source Xclk FOSC2 FOSC1 FOSC0 RTCS10UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency Divm Cclk Undefined RC Oscillator/DIVMWDT Oscillator/DIVM External clock/DIVM Changing RTCS1-0 Reset Sources Affecting the REAL-TIME ClockREAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Power Reduction Modes POWER-ON DetectionBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Uart Modes Updating the BRGR1 and BRGR0 Sfrs SFR SpaceBaud Rate Generator and Selection SFR Locations for UARTs Break Detect Framing ErrorBrgcon Scon More about Uart Mode Sstat Serial Port Mode 0 Double Buffering Must Be Disabled More about Uart Modes 2 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 PCON.6 RB8 SMOD0 Double Buffering Double Buffering in Different Modes 9TH BIT BIT 8 in Double Buffering Modes 1, 2 Transmission with and without Double Buffering Multiprocessor Communications Automatic Address Recognition Uart Uart POWER-ON Reset Code Execution Block Diagram of Reset Rstsrc Comparator Configuration Comparator Interrupt Comparator and Power Reduction ModesInternal Reference Voltage CIN1A CO1 CMP1 Cmpref Comparator Configuration Example Analog Comparators Kbpatn Kbcon Kbmask Watchdog Function Watchdog timer configurationWdte Wdse Function Feed Sequence Wdcon P89LPC906/907/908 Watchdog Timeout Values PRE2-PRE0 Watchdog Watchdog Timer in Timer ModePrescaler Reset Pclk Control register Prescaler Power Down OperationWatchdog Clock Source CLK Watchdog Timer Watchdog Timer Dual Data Pointers Software ResetAUXR1 MOVXA, @DPTR MOVCA, @A+DPTRMove code byte relative to Dptr to the accumulator MOVX@DPTR, a General Description FeaturesUsing Flash AS Data Storage Introduction to IAP-LITE Flash Program Memory Fmcon Accessing Additional Flash Elements Assembly language routine to erase/program all or part of a Reading Additional Flash Elements ERASE-PROGRAMMING Additional Flash ElementsUCFG1 Fmadrl Conf UCFG1 User Configuration BytesP89LPC906 Address xxxxh User Security BytesSECx Unprogrammed value 00h Bootvec Bootstat Arithmetic Logical Mnemonic Description Bytes Cycles Hex Code Data Transfer Boolean Branching D8-DF RetiB8-BF Miscellaneous 2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908