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P89LPC908, P89LPC906, P89LPC907
user manual
Power Monitoring Functions
Models:
P89LPC907
P89LPC908
P89LPC906
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Block Diagram P89LPC906
Framing Error
CPU Clock Cclk Wakeup Delay
Logic Symbols
PIN Configurations
Power-On reset code execution
LOW Power Select P89LPC906
Bootvec
Features
Overflows. Mode
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Philips Semiconductors
User’s Manual - Preliminary -
POWER MONITORING FUNCTIONS
P89LPC906/907/908
2003 Dec 8
58
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Contents
User Manual
Table of Contents
Brownout Detection Power-On Detection Power Reduction Modes
Power-On reset code execution
103
List of Figures
List of Figures
PIN Configurations
P89LPC906
Logic Symbols
Product Comparison
CPU
Block Diagram P89LPC906
KB Code Flash
Oscillator Divider
Byte Data RAM
Block Diagram P89LPC907
Uart
Clock
Block Diagram P89LPC908
Data RAM Port
PIN Descriptions P89LPC906
TxD
PIN Descriptions P89LPC907
P1.0
P1.2
P1.1
PIN Descriptions P89LPC908
Keyboard Input P1.0 P1.5
RxD
Special function registers
Special function registers table P89LPC906
MSB LSB
Hex
Special function registers table P89LPC907
CMP1 Cmpref
TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON#
Special function registers table P89LPC908
KB2 KB6 KB5 KB4
TL0
SFR
Memory Organization
Data
Code
CPU Clock Oscclk
Enhanced CPU
Clock Definitions
LOW Speed Oscillator Option P89LPC906
ON-CHIP RC Oscillator Option
Oscillator Option SELECTION- P89LPC906
Clock Output P89LPC906
Watchdog Oscillator Option
External Clock Input Option P89LPC906
CPU Clock Cclk Wakeup Delay
BIT Symbol Function
CPU Clock Cclk Modification Divm Register
Med freq
LOW Power Select P89LPC906
High freq
Low freq
CPU
Clocks
Summary of Interrupts P89LPC906 Description
Flag Bits Address Enable Bits Priority Ranking
Interrupt Priority Structure
Interrupt Arbitration
Summary of Interrupts P89LPC907,P89LPC908 Description
External Interrupt Inputs
External Interrupt PIN Glitch Suppression
TI & RI
Bopd EBO Rtcf Kbif
Interrupts
Number of I/O Pins Available Clock Source Reset Option
Port Configurations
QUASI-BIDIRECTIONAL Output Configuration
RST
Open Drain Output Configuration
Port latch data
Port 0 Analog Functions
INPUT-ONLY Configuration
PUSH-PULL Output Configuration
Strong Port latch data Port pin Input data Glitch rejection
Port Output Configuration P89LPC907
Port Output Configuration P89LPC906
Port Output Configuration P89LPC908
Ports
Ports
TMOD.6
Tmod
TMOD.7
TMOD.3
Tamod P89LPC907
Overflows. Mode
Mode
TAMOD.7-1
Tcon
T0C/T = Overflow
Pclk
T0C/T = Overflow TLn THn TFn Interrupt T0 Pin
THn TFn
Pclk TL0
Timer Overflow Toggle Output P89LPC907
TR0 ENT0 Pclk TH0
Timers 0
REAL-TIME Clock Source
Xclk
FOSC2 FOSC1 FOSC0 RTCS10
UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency
Divm Cclk
Undefined
RC Oscillator/DIVM
WDT Oscillator/DIVM
External clock/DIVM
Changing RTCS1-0
Reset Sources Affecting the REAL-TIME Clock
REAL-TIME Clock INTERRUPT/WAKE UP
Rtccon
REAL-TIME CLOCK/SYSTEM Timer
Brownout Detection
Power Reduction Modes
POWER-ON Detection
Brownout Options
Power Reduction Modes
Pcon
Pcona
Power Monitoring Functions
Uart
Modes
Updating the BRGR1 and BRGR0 Sfrs
SFR Space
Baud Rate Generator and Selection
SFR Locations for UARTs
Break Detect
Framing Error
Brgcon
Scon
More about Uart Mode
Sstat
Serial Port Mode 0 Double Buffering Must Be Disabled
More about Uart Modes 2
Framing Error and RI in Modes 2 and 3 with SM2 =
FE and RI when SM2 = 1 in Modes 2
PCON.6 RB8 SMOD0
Double Buffering
Double Buffering in Different Modes
9TH BIT BIT 8 in Double Buffering Modes 1, 2
Transmission with and without Double Buffering
Multiprocessor Communications
Automatic Address Recognition
Uart
Uart
POWER-ON Reset Code Execution
Block Diagram of Reset
Rstsrc
Comparator Configuration
Comparator Interrupt
Comparator and Power Reduction Modes
Internal Reference Voltage
CIN1A CO1 CMP1 Cmpref
Comparator Configuration Example
Analog Comparators
Kbpatn
Kbcon
Kbmask
Watchdog Function
Watchdog timer configuration
Wdte Wdse Function
Feed Sequence
Wdcon
P89LPC906/907/908 Watchdog Timeout Values
PRE2-PRE0
Watchdog
Watchdog Timer in Timer Mode
Prescaler Reset Pclk
Control register
Prescaler
Power Down Operation
Watchdog Clock Source
CLK
Watchdog Timer
Watchdog Timer
Dual Data Pointers
Software Reset
AUXR1
MOVXA, @DPTR
MOVCA, @A+DPTR
Move code byte relative to Dptr to the accumulator
MOVX@DPTR, a
General Description
Features
Using Flash AS Data Storage
Introduction to IAP-LITE
Flash Program Memory
Fmcon
Accessing Additional Flash Elements
Assembly language routine to erase/program all or part of a
Reading Additional Flash Elements
ERASE-PROGRAMMING Additional Flash Elements
UCFG1
Fmadrl
Conf
UCFG1
User Configuration Bytes
P89LPC906
Address xxxxh
User Security Bytes
SECx
Unprogrammed value 00h
Bootvec
Bootstat
Arithmetic
Logical
Mnemonic Description Bytes Cycles Hex Code
Data Transfer
Boolean
Branching
D8-DF
Reti
B8-BF
Miscellaneous
2003 Dec Initial release
104
Index
Dual Data Pointers
Port 0 12, 13
SFR
109
P89LPC906/907/908
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