Msb Lsb | Philips P89LPC908, P89LPC906, P89LPC907 instruction

Philips Semiconductors

User’s Manual - Preliminary -

GENERAL DESCRIPTION

P89LPC906/907/908

Name

Description

SFR

Bit Functions and Addresses

Reset Value

Address

MSB

LSB

Hex

Binary

00H1

IP1H#

Interrupt Priority 1 High

F7H

-

-

-

-

-

PCH

PKBIH

-

00x00000

KBCON#

Keypad Control Register

94H

-

-

-

-

-

-

PATN_S

KBIF

00H1

xxxxxx00

EL

KBMASK#

Keypad Interrupt Mask Register

86H

00H

00000000

KBPATN#

Keypad Pattern Register

93H

FFH

11111111

87

86

85

84

83

82

81

80

P0*

Port 0

80H

-

CMP1/

CMPREF/

CIN/1A

-

-

-

-

Note 1

KB6

KB5

KB4

97

96

95

94

93

92

91

90

P1*

Port 1

90H

-

-

RST

-

-

-

-

-

B7

B6

B5

B4

B3

B2

B1

B0

P3*

Port 3

B0H

-

-

-

-

-

-

XTAL1

XTAL2

Note 1

P0M1#

Port 0 Output Mode 1

84H

-

(P0M1.6)

(P0M1.5)

(P0M1.4)

-

-

-

-

FFH

11111111

P0M2#

Port 0 Output Mode 2

85H

-

(P0M2.6)

(P0M2.5)

(P0M2.4)

-

-

-

-

00H

00000000

FFH1

11111111

P1M1#

Port 1 Output Mode 1

91H

-

-

(P1M1.5)

-

-

-

-

-

P1M2#

Port 1 Output Mode 2

92H

-

-

(P1M2.5)

-

-

-

-

-

00H1

00000000

P3M1#

Port 3 Output Mode 1

B1H

-

-

-

-

-

-

(P3M1.1)

(P3M1.0)

03H1

xxxxxx11

P3M2#

Port 3 Output Mode 2

B2H

-

-

-

-

-

-

(P3M2.1)

(P3M2.0)

00H1

xxxxxx00

PCON#

Power Control Register

87H

-

-

BOPD

BOI

GF1

GF0

PMOD1

PMOD0

00H

00000000

00H1

00000000

PCONA#

Power Control Register A

B5H

RTCPD

-

VCPD

-

-

-

-

-

D7

D6

D5

D4

D3

D2

D1

D0

PSW*

Program Status Word

D0H

CY

AC

F0

RS1

RS0

OV

F1

P

00H

00000000

PT0AD#

Port 0 Digital Input Disable

F6H

-

-

PT0AD.5

PT0AD.4

-

-

-

-

00H

xx00000x

RSTSRC#

Reset Source Register

DFH

-

-

BOF

POF

-

R_WD

R_SF

R_EX

Note 2

60H1,5

011xxx00

RTCCON#

Real-Time Clock Control

D1H

RTCF

RTCS1

RTCS0

-

-

-

ERTC

RTCEN

RTCH#

Real-Time Clock Register High

D2H

00H5

00000000

RTCL#

Real-Time Clock Register Low

D3H

00H5

00000000

SP

Stack Pointer

81H

07H

00000111

TAMOD#

Timer 0 Auxiliary Mode

8FH

-

-

-

-

-

-

-

T0M2

00H

xxx0xxx0

8F

8E

8D

8C

8B

8A

89

88

TCON*

Timer 0 and 1 Control

88H

TF1

TR1

TF0

TR0

-

-

-

-

00H

00000000

2003 Dec 8

16

Image 16

Philips P89LPC908, P89LPC906, P89LPC907 user manual Msb Lsb

Contents

User Manual Table of Contents Brownout Detection Power-On Detection Power Reduction Modes Power-On reset code execution 103 List of Figures List of Figures PIN Configurations P89LPC906 Logic Symbols Product Comparison Block Diagram P89LPC906 KB Code FlashCPU Oscillator Divider Block Diagram P89LPC907 UartByte Data RAM Clock Block Diagram P89LPC908 Data RAM Port PIN Descriptions P89LPC906 PIN Descriptions P89LPC907 P1.0TxD P1.2 PIN Descriptions P89LPC908 Keyboard Input P1.0 P1.5P1.1 RxD Special function registers Special function registers table P89LPC906 MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Memory Organization DataSFR Code Enhanced CPU Clock DefinitionsCPU Clock Oscclk LOW Speed Oscillator Option P89LPC906 Oscillator Option SELECTION- P89LPC906 Clock Output P89LPC906ON-CHIP RC Oscillator Option Watchdog Oscillator Option CPU Clock Cclk Wakeup Delay BIT Symbol FunctionExternal Clock Input Option P89LPC906 CPU Clock Cclk Modification Divm Register LOW Power Select P89LPC906 High freqMed freq Low freq CPU Clocks Flag Bits Address Enable Bits Priority Ranking Interrupt Priority StructureSummary of Interrupts P89LPC906 Description Interrupt Arbitration External Interrupt Inputs External Interrupt PIN Glitch SuppressionSummary of Interrupts P89LPC907,P89LPC908 Description TI & RI Bopd EBO Rtcf Kbif Interrupts Port Configurations QUASI-BIDIRECTIONAL Output ConfigurationNumber of I/O Pins Available Clock Source Reset Option RST Open Drain Output Configuration Port latch data INPUT-ONLY Configuration PUSH-PULL Output ConfigurationPort 0 Analog Functions Strong Port latch data Port pin Input data Glitch rejection Port Output Configuration P89LPC907 Port Output Configuration P89LPC906Port Output Configuration P89LPC908 Ports Ports Tmod TMOD.7TMOD.6 TMOD.3 Overflows. Mode ModeTamod P89LPC907 TAMOD.7-1 Tcon Pclk T0C/T = Overflow TLn THn TFn Interrupt T0 PinT0C/T = Overflow THn TFn Pclk TL0 Timer Overflow Toggle Output P89LPC907TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source FOSC2 FOSC1 FOSC0 RTCS10 UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock FrequencyXclk Divm Cclk RC Oscillator/DIVM WDT Oscillator/DIVMUndefined External clock/DIVM Changing RTCS1-0 Reset Sources Affecting the REAL-TIME ClockREAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Power Reduction Modes POWER-ON DetectionBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Uart Modes SFR Space Baud Rate Generator and SelectionUpdating the BRGR1 and BRGR0 Sfrs SFR Locations for UARTs Break Detect Framing ErrorBrgcon Scon More about Uart Mode Sstat Serial Port Mode 0 Double Buffering Must Be Disabled Framing Error and RI in Modes 2 and 3 with SM2 = FE and RI when SM2 = 1 in Modes 2More about Uart Modes 2 PCON.6 RB8 SMOD0 Double Buffering Double Buffering in Different Modes 9TH BIT BIT 8 in Double Buffering Modes 1, 2 Transmission with and without Double Buffering Multiprocessor Communications Automatic Address Recognition Uart Uart POWER-ON Reset Code Execution Block Diagram of Reset Rstsrc Comparator Configuration Comparator and Power Reduction Modes Internal Reference VoltageComparator Interrupt CIN1A CO1 CMP1 Cmpref Comparator Configuration Example Analog Comparators Kbpatn Kbcon Kbmask Watchdog Function Watchdog timer configurationWdte Wdse Function Feed Sequence Wdcon P89LPC906/907/908 Watchdog Timeout Values PRE2-PRE0 Watchdog Timer in Timer Mode Prescaler Reset PclkWatchdog Control register Power Down Operation Watchdog Clock SourcePrescaler CLK Watchdog Timer Watchdog Timer Dual Data Pointers Software ResetAUXR1 MOVCA, @A+DPTR Move code byte relative to Dptr to the accumulatorMOVXA, @DPTR MOVX@DPTR, a Features Using Flash AS Data StorageGeneral Description Introduction to IAP-LITE Flash Program Memory Fmcon Accessing Additional Flash Elements Assembly language routine to erase/program all or part of a Reading Additional Flash Elements ERASE-PROGRAMMING Additional Flash ElementsUCFG1 Fmadrl Conf UCFG1 User Configuration BytesP89LPC906 User Security Bytes SECxAddress xxxxh Unprogrammed value 00h Bootvec Bootstat Arithmetic Logical Mnemonic Description Bytes Cycles Hex Code Data Transfer Boolean Branching Reti B8-BFD8-DF Miscellaneous 2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908