Uart | Philips P89LPC906, P89LPC908, P89LPC907 guide

Philips Semiconductors	User’s Manual - Preliminary -

UART	P89LPC906/907/908

since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000.

In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0:

Slave 0	SADDR = 1100		0000
	SADEN = 1111		1001
	Given	= 1100	0XX0
Slave 1	SADDR = 1110		0000
	SADEN = 1111		1010
	Given	= 1110	0X0X
Slave 2	SADDR = 1110		0000
	SADEN = 1111		1100
	Given	= 1110	00XX

In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are treated as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR and SADEN are loaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature.

2003 Dec 8

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Philips P89LPC906, P89LPC908, P89LPC907 user manual Uart

Contents

User Manual Table of Contents Power-On reset code execution Brownout Detection Power-On Detection Power Reduction Modes 103 List of Figures List of Figures P89LPC906 PIN Configurations Product Comparison Logic Symbols KB Code Flash Block Diagram P89LPC906CPU Oscillator Divider Uart Block Diagram P89LPC907Byte Data RAM Clock Data RAM Port Block Diagram P89LPC908 PIN Descriptions P89LPC906 P1.0 PIN Descriptions P89LPC907TxD P1.2 Keyboard Input P1.0 P1.5 PIN Descriptions P89LPC908P1.1 RxD Special function registers table P89LPC906 Special function registers MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Data Memory OrganizationSFR Code Clock Definitions Enhanced CPUCPU Clock Oscclk LOW Speed Oscillator Option P89LPC906 Clock Output P89LPC906 Oscillator Option SELECTION- P89LPC906ON-CHIP RC Oscillator Option Watchdog Oscillator Option BIT Symbol Function CPU Clock Cclk Wakeup DelayExternal Clock Input Option P89LPC906 CPU Clock Cclk Modification Divm Register High freq LOW Power Select P89LPC906Med freq Low freq CPU Clocks Interrupt Priority Structure Flag Bits Address Enable Bits Priority RankingSummary of Interrupts P89LPC906 Description Interrupt Arbitration External Interrupt PIN Glitch Suppression External Interrupt InputsSummary of Interrupts P89LPC907,P89LPC908 Description TI & RI Bopd EBO Rtcf Kbif Interrupts QUASI-BIDIRECTIONAL Output Configuration Port ConfigurationsNumber of I/O Pins Available Clock Source Reset Option RST Port latch data Open Drain Output Configuration PUSH-PULL Output Configuration INPUT-ONLY ConfigurationPort 0 Analog Functions Strong Port latch data Port pin Input data Glitch rejection Port Output Configuration P89LPC906 Port Output Configuration P89LPC907Port Output Configuration P89LPC908 Ports Ports TMOD.7 TmodTMOD.6 TMOD.3 Mode Overflows. ModeTamod P89LPC907 TAMOD.7-1 Tcon T0C/T = Overflow TLn THn TFn Interrupt T0 Pin PclkT0C/T = Overflow THn TFn Timer Overflow Toggle Output P89LPC907 Pclk TL0TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency FOSC2 FOSC1 FOSC0 RTCS10Xclk Divm Cclk WDT Oscillator/DIVM RC Oscillator/DIVMUndefined External clock/DIVM Reset Sources Affecting the REAL-TIME Clock Changing RTCS1-0REAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection POWER-ON Detection Power Reduction ModesBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Modes Uart Baud Rate Generator and Selection SFR SpaceUpdating the BRGR1 and BRGR0 Sfrs SFR Locations for UARTs Framing Error Break DetectBrgcon Scon Sstat More about Uart Mode Serial Port Mode 0 Double Buffering Must Be Disabled FE and RI when SM2 = 1 in Modes 2 Framing Error and RI in Modes 2 and 3 with SM2 =More about Uart Modes 2 PCON.6 RB8 SMOD0 Double Buffering in Different Modes Double Buffering Transmission with and without Double Buffering 9TH BIT BIT 8 in Double Buffering Modes 1, 2 Automatic Address Recognition Multiprocessor Communications Uart Uart Block Diagram of Reset POWER-ON Reset Code Execution Rstsrc Comparator Configuration Internal Reference Voltage Comparator and Power Reduction ModesComparator Interrupt CIN1A CO1 CMP1 Cmpref Comparator Configuration Example Analog Comparators Kbcon Kbpatn Kbmask Watchdog timer configuration Watchdog FunctionWdte Wdse Function Feed Sequence Wdcon PRE2-PRE0 P89LPC906/907/908 Watchdog Timeout Values Prescaler Reset Pclk Watchdog Timer in Timer ModeWatchdog Control register Watchdog Clock Source Power Down OperationPrescaler CLK Watchdog Timer Watchdog Timer Software Reset Dual Data PointersAUXR1 Move code byte relative to Dptr to the accumulator MOVCA, @A+DPTRMOVXA, @DPTR MOVX@DPTR, a Using Flash AS Data Storage FeaturesGeneral Description Introduction to IAP-LITE Flash Program Memory Fmcon Assembly language routine to erase/program all or part of a Accessing Additional Flash Elements ERASE-PROGRAMMING Additional Flash Elements Reading Additional Flash ElementsUCFG1 Fmadrl Conf User Configuration Bytes UCFG1P89LPC906 SECx User Security BytesAddress xxxxh Unprogrammed value 00h Bootstat Bootvec Logical Arithmetic Data Transfer Mnemonic Description Bytes Cycles Hex Code Branching Boolean B8-BF RetiD8-DF Miscellaneous 2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908