Sony Ericsson GM48, GM47 manual bit word within 24-bit frame

GM47/GM48 INTEGRATOR’S MANUAL

PCM Timing Diagrams

The PCM timing is shown in Figure 2.6 below and it is seen that the CPU has 45µs to serve an interrupt and setup data channels. Data is sent on the falling edge of the sync pulse. The data bits in PCMULD and PCMDLD are aligned so that the MSB in each word occurs on the same clock edge as shown in Figure 2.7.

Clk

125 µs

Sync

45 µs

Data

Figure 2.6 16-bit word within 24-bit frame

PCM signal timing is shown in Figure 2.7. The signals characteristics are described in the tables following Figure 2.7.

PCMCLK

tPSS

PCMSYN

tPSH

tDSL

PCMIN

MSB

PCMOUT X MSB

tDSH

D14

tPDLP

D14

D13

D13

Figure 2.7 PCM Timing Diagram

Name	Description	Typ.	Unit
tPSS	PCMSYN (setup) to PCMCLK (fall)	2.5	µs
tPSH	PCMSYN pulse length	5	µs
tDSL	PCMI (setup) to PCMCLK (fall)	2.5	µs
tDSH	PCMI (hold) from PCMCLK (fall)	2.5	µs
tPDLP	PCMO valid from PCMCLK (rise)	2.5	µs
Name	Description	Typ.	Unit
FPCMCLK	PCM clock frequency	200	kHz
TPCMCLK	PCM clock period with 50/50 mark space ratio	5	µs
FPCMSYN	PCM sync frequency	8	kHz

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