Tests and Diagnostics
With regard to the test memory content, save the data to the test memory before the test and restore it to the former address after the test. (Coincidence assurance of the memory content)
Details of Test
Step 1: Sequential Write (Fixed pattern 1 MMX version 00005555AAAAFFFFh） : Sequential Read and Compare
Step 3: Sequential Write (Fixed pattern 2 MMX version FFFFAAAA55550000h）
: Sequential Read and Compare
Step 5: JMP + Write (Address pattern 1) 0, 1/2 increment 1//4, 3/4 decrement : JMP + Read and Compare
Step 7: JMP＋Write (Address pattern 2) 1/4. 3/4 increment 0, 1/2 decrement
:JMP＋Read and Compare
3)Cache memory (On / off)
This subtest writes constant data to constant address 70000h in the protected mode, then reads the written data and compares the result with the original data.
With regard to the test memory content, save the data to the test memory before the test and restore it to the former address after the test. (Coincidence assurance of the memory content) Details of Test:
This subtest displays the number of memory accesses within the same time in both of Cache ON and Cache OFF by the counter. Check that the benchmark speed is high when the cache is used
4) Stress
This subtest writes or reads constant data and address data from 1MB to the maximum MB in the protected mode and compare the results with the original data.
For the content of the test memory, save the data to the test target memory before the test and restore it to the former address after the test.
Details of Test:
This subtest is performed once from step 1 to step 3 and repeated 20 times from step 5 to step 8 and then it displays the total number of the test performances as Sub Step Number.
Step 1: Sequential Write (Fixed pattern 1 MMX version 00005555AAAAFFFFh） : Sequential Read and Compare
Step 3: Sequential Write (Fixed pattern 2 MMX version FFFFAAAA55550000h） : Sequential Read and Compare
Step 5: JMP + Write (Address pattern 1) 0, 1/2 increment 1/4, 3/4 decrement
