Intel 8XC196MD manuals
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2 We Value Your Opinion24 CHAPTER 1 GUIDE TO THIS MANUAL29 1-6Table 1-1. Handbooks and Product Information Table 1-2. Application Notes, Application Briefs, and Article Reprints 30 1-7GUIDE TO THIS MANUAL Table 1-3. MCS 96 Microcontroller Datasheets (Commercial/Express) Table 1-4. MCS 96 Microcontroller Datasheets (Automotive) Table 1-2. Application Notes, Application Briefs, and Article Reprints (Continued) 38 CHAPTER 2 ARCHITECTURAL OVERVIEW39 2-2Table 2-1. Features of the 8XC196M Product Family 40 2-3ARCHITECTURAL OVERVIEW Figure 2-2. Block Diagram of the Core Figure 2-1. 8XC196M Block Diagram 3-1 52 CHAPTER 3 PROGRAMMING CONSIDERATIONSNOTE Table 3-1. Operand Type Definitions 56 62 66 CHAPTER 4 MEMORY PARTITIONS88 CHAPTER 5 STANDARD AND PTS INTERRUPTS89 5-2Figure 5-1. Flow Diagram for PTS and Standard Interrupts 90 5-3Table 5-1. Interrupt Signals Table 5-2. Interrupt and PTS Control and Status Registers 92 5-5Table 5-3. Interrupt Sources, Vectors, and Priorities 95 5-8x Figure 5-3. Flow Diagram for the OVRTM Interrupt 96 97 98 5-11Figure 5-4. Standard Interrupt Response Time 5.4.2.2 PTS Interrupt Latency Figure 5-5. PTS Interrupt Response Time 101 5-14Figure 5-6. PTS Select (PTSSEL) Register 102 5-15Figure 5-7. Interrupt Mask (INT_MASK) Register 103 5-16Figure 5-8. Interrupt Mask 1 (INT_MASK1) Register 104 5-17Figure 5-9. Peripheral Interrupt Mask (PI_MASK) Register 105 5-18Figure 5-9. Peripheral Interrupt Mask (PI_MASK) Register (Continued) 108 5-21Figure 5-10. Interrupt Pending (INT_PEND) Register 109 5-22Figure 5-11. Interrupt Pending 1 (INT_PEND1) Register 110 5-23Figure 5-12. Peripheral Interrupt Pending (PI_PEND) Register 111 5-24Figure 5-12. Peripheral Interrupt Pending (PI_PEND) Register (Continued) 113 5-26Figure 5-14. PTS Service (PTSSRV) Register 115 5-28Figure 5-16. PTS Control Block Single Transfer Mode 116 5-29Figure 5-16. PTS Control Block Single Transfer Mode (Continued) 118 5-31Figure 5-17. PTS Control Block Block Transfer Mode 119 5-32Figure 5-17. PTS Control Block Block Transfer Mode (Continued) 120 5-33Figure 5-18. PTS Control Block A/D Scan Mode 125 5-38Figure 5-19. PTS Control Block 1 Serial I/O Mode 126 5-39Figure 5-19. PTS Control Block 1 Serial I/O Mode (Conti nued) 128 5-41Figure 5-20. PTS Control Block 2 Serial I/O Mode 129 5-42Figure 5-20. PTS Control Block 2 Serial I/O Mode (Conti nued) 134 138 141 5-54Figure 5-26. Asynchronous SIO Transmit Mode End-of-PTS Interrupt Routine Flowchart 142 145 5-58Figure 5-28. Asynchronous SIO Receive Mode End-of-PTS Interrupt Routine Flowchart 148 CHAPTER 6 I/O PORTS150 6-3Figure 6-1. Standard Input-only Port Structure Table 6-3. Input-only Port Registers 152 6-5Table 6-4. Bidirectional Port Pins 153 6-6Table 6-5. Bidirectional Port Control and Status Registers 155 6-8Figure 6-2. Bidirectional Port Structure 6-9 156 Table 6-6. Logic Table for Bidirectional Ports in I/O Mode Table 6-7. Logic Table for Bidirectional Ports in Special-function Mode 158 6-11Table 6-8. Control Register Values for Each Configuration Table 6-9. Port Configuration Example 165 6-18Figure 6-4. Output-only Port Figure 6-5. Port 6 Output Configuration (WG_OUTPUT) Register 166 6-19Figure 6-5. Port 6 Output Configuration (WG_OUTPUT) Register (Continued) 170 CHAPTER 7 SERIAL I/O (SIO) PORT171 7-2Table 7-1. Serial Port Signals Table 7-2. Serial Port Control and Status Registers 172 7-3Table 7-2. Serial Port Control and Status Registers (Continued) 173 7-4Table 7-2. Serial Port Control and Status Registers (Continued) 175 180 7-11_CON) Register (Continued) Figure 7-6. Serial Port Control (SP 181 7-12_BAUD) Register Baud Rate (SP Figure 7-7. Serial Port WARNING 182 7-13_BAUD) Register (Continued) Baud Rate (SP Figure 7-7. Serial Port 184 7-15_STATUS) Register (SP Figure 7-8. Serial Port Status 188 CHAPTER 8 FREQUENCY GENERATOR189 8-2Table 8-1. Frequency Generator Signal Table 8-2. Frequency Generator Control and Status Registers 192 8-5Figure 8-4. Infrared Remote Control Application Block Diagram 40 kHz Zero = 2 ms One = 4 ms Figure 8-5. Data Encoding Exam ple 193 8-6194 8-7195 8-8196 8-9200 CHAPTER 9 WAVEFORM GENERA TOR201 9-2Figure 9-1. Waveform Generator Block Diagram 202 9-3Table 9-1. Waveform Generator Signals Table 9-2. Waveform Generator Control and Status Registers 207 9-8Table 9-3. Operation in Center-aligned and Edge-aligned Modes Table 9-4. Register Updates 210 9-11Figure 9-6. Edge-aligned Modes Counter Operation Figure 9-7. Edge-aligned Modes Output Operation x Note: Carrier period and duty cycle both change since WG_COMP is not changed. 212 9-13Figure 9-8. WG Output Configuration (WG_OUTPUT) Register 213 9-14Figure 9-8. WG Output Configuration ( WG_OUTPUT) Register (Continued) 214 9-15Figure 9-9. Waveform Generator Protection (WG_PROTECT) Register 215 9-16Figure 9-10. Waveform Generator Reload (WG_RELOAD) Register 216 9-17) Register Figure 9-11. Phase Compare (WG_COMP 217 9-18Figure 9-12. Waveform Generator Control (WG_CONTROL) Register 221 9-22222 9-23223 9-24224 9-25228 CHAPTER 10 PULSE-WIDTH MODULAT OR229 10-2Figure 10-1. PWM Block Diagram Table 10-1. PWM SignalsPort Pin PWM Signal PWM R S Q Port 6 Control 10-5 PULSE-WIDTH MODULATOR 232 where:Table 10-3. PWM Output Frequencies (FPWM) 10-6 233 where:Figure 10-3. PWM Period (PWM_PERIOD) Regi ster 236 10-9PULSE-WIDTH MODULATOR Figure 10-6. Waveform Generator Output Configuration (WG_OUTPUT) Register 237 10-10Figure 10-8. PWM to Analog Conversion Circuitry Figure 10-7. D/A Buffer Block Diagram 240 CHAPTER 11 EVENT PROCESSOR ARRAY (EPA)11-2 Figure 11-1. EPA Block Diagram Table 11-2. EPA and Timer/Counter Signals 241 Notes: For the 8XC196MC, = 3. For the 8XC196MD, = 5. For the 8XC196MH, 242 11-3Table 11-3. EPA Control and Status Registers Table 11-2. EPA and Timer/Counter Signals (Continued) 243 11-4Table 11-3. EPA Control and Status Registers (Continued) 244 11-5Table 11-3. EPA Control and Status Registers (Continued) 245 11-6Figure 11-2. EPA Timer/Counters----------------------------------------------------------- resolution = 4prescaler_divisor F 247 11-8Figure 11-3. Quadrature Mode Interface Table 11-4. Quadrature Mode Truth Table 248 251 252 266 CHAPTER 12 ANALOG-TO-DIGITAL (A/D) CONVER TER267 12-2Table 12-1. A/D Converter Pins Table 12-2. A/D Control and Status Registers 269 272 12-7ANALOG-TO-DIGITAL (A/D) CONVERTER Figure 12-4. A/D Time (AD_TIME) Register 273 12-8Figure 12-5. A/D Command (AD_COMMAND) Register 274 12-9ANALOG-TO-DIGITAL (A/D) CONVERTER Figure 12-6. A/D Result (AD_RESULT) Register Read Format 280 283 12-18Figure 12-11. Terminal-based A/D Conversion Characteristic 13-1 286 CHAPTER 13 MINIMUM HARDWARE CONSIDERATIONSTable 13-1. Minimum Required Signals 288 13-3MINIMUM HARDWARE CONSIDERATIONS Figure 13-1. Minimum Hardware Connections 293 13-8Figure 13-7. Reset Timing Sequence 294 296 13-11MINIMUM HARDWARE CONSIDERATIONS Figure 13-11. Example of a System Reset Circuit Figure 13-10. Minimum Reset Circuit 302 CHAPTER 14 SPECIAL OPERATING MODES303 14-2Table 14-2. Operating Mode Control and Status Registers Table 14-1. Operating Mode Control Signals (Continued) 304 14-3SPECIAL OPERATING MODES Table 14-2. Operating Mode Control and Status Registers (Continued) 307 310 14-9SPECIAL OPERATING MODES Figure 14-4. Typical Voltage on the VPP Pin While Exiting Powerdown , Volts 316 CHAPTER 15 INTERFACING WITH EXTERNAL MEMORY317 15-2318 15-3319 15-4Table 15-2. External Memory Interface Registers 320 15-5Table 15-3. Register Settings for Configuring External Memory Interfac e Signals Table 15-2. External Memory Interface Registers (Continued) 322 15-7Figure 15-1. Chip Configuration 0 (CCR0) Register 323 15-8Figure 15-1. Chip Configuration 0 (CCR0) Register (Continued) 324 15-9Figure 15-2. Chip Configuration 1 (CCR1) Register 325 15-10Figure 15-2. Chip Configuration 1 (CCR1) Register 327 15-12Figure 15-4. BUSWIDTH Timing Diagram (8XC196MC, MD) Figure 15-5. BUSWIDTH Timing Diagram (8XC196MH) The CLKOUT pin is available only on the 8XC196MC, MD. 330 15-15Figure 15-6. Timings for 16-bit Buses The CLKOUT pin is available only on the 8XC196MC, MD. 334 15-19Figure 15-8. READY Timing Diagram One Wait State (8XC196MC, M D) The CLKOUT pin is available only on the 8XC196MC, MD. 335 15-20336 15-21Table 15-6. Bus-control Modes Table 15-5. READY Signal Timing Definitions (Continued) 338 15-23Figure 15-12. 8-bit System with Flash and RAM 339 15-24Figure 15-13. 16-bit System with Dynamic Bus Width 341 15-26Figure 15-15. 16-bit System with Writes to Byte-wide RAMs 344 15-29Figure 15-19. 16-bit System with EPROM 346 15-31Figure 15-21. 16-bit System with RAM 347 15-32Figure 15-22. System Bus Timing The CLKOUT pin is available only on the 8XC196MC, MD. 349 15-34Table 15-9. Microcontroller Meets These Specifications 350 15-35Table 15-9. Microcontroller Meets These Specifications (Continued) 354 CHAPTER 16 PROGRAMMING THE NONVOLAT ILE ME MO RY355 357 360 16-7Figure 16-1. Unerasable PROM (USFR) Register Table 16-4. UPROM Programming Values and Locations for Slave Mode 364 16-11Figure 16-4. Pin Functions in Programming Modes Table 16-6. Pin Descriptions 365 16-12Table 16-6. Pin Descriptions (Continued) 367 369 16-16Figure 16-5. Slave Programming Circuit Table 16-8. Device Signature Word and Programming Voltages 371 16-18Figure 16-6. Chip Configuration Registers (CCRs) 373 16-20Figure 16-7. Address/Command Decoding Routine 374 16-21Figure 16-8. Program Word Routine 375 16-22Measure from falling edge of last PROG# pulse in sequence. Figure 16-9. Program Word Waveform Additional program pulses and verifications. 376 16-23Figure 16-10. Dump Word Routine 377 16-24Figure 16-11. Dump Word Waveform Table 16-10. Timing Mnemonics 379 16-26Figure 16-12. Auto Programming Circuit 381 16-28Figure 16-13. Auto Programming Routine 384 16-31Figure 16-14. PCCB and UPROM Programming Circuit 386 16-33Figure 16-15. Run-time Programming Code Example 390 APPENDIX A INSTRUCTION SET REFERENCE450 APPENDIX B SIGNAL DESCRIPTIONS451 B-2Table B-2. 8XC196MC Signals Arranged by Functional Categories 452 B-3Figure B-1. 8XC196MC 64-lead Shrink DIP (SDIP) PackageU8XC196MC View of component as mounted on PC board 453 B-4Figure B-2. 8XC196MC 84-lead PLCC Packagex8XC196MC View of component as mounted on PC board 454 B-5Figure B-3. 8XC196MC 80-lead Shrink EIAJ/QFP Packagex8XC196MC View of component as mounted on PC board 455 B-6Table B-3. 8XC196MD Signals Arranged by Functional Categories 456 B-7Figure B-4. 8XC196MD 84-lead PLCC Packagex8XC196MD View of component as mounted on PC board 457 B-8Figure B-5. 8XC196MD 80-lead Shrink EIAJ/QFP Packagex8XC196MD View of component as mounted on PC board 458 B-9Table B-4. 8XC196MH Signals Arranged by Functional Categories 459 B-10Figure B-6. 8XC196MH 64-lead Shrink DIP (SDIP) Packagex8XC196MH View of component as mounted on PC board 460 B-11Figure B-7. 8XC196MH 84-lead PLCC Packagex8XC196MH View of component as mounted on PC board 461 B-12Figure B-8. 8XC196MH 80-lead Shrink EIAJ/QFP Package x8XC196MH View of component as mounted on PC board 462 B-13Table B-5. Description of Columns of Table B-6 Table B-6. Signal Descriptions 463 B-14464 B-15465 B-16466 B-17467 B-18468 B-19469 B-20470 B-21471 B-22472 B-23Table B-7. Definition of Status Symbols Table B-8. 8XC196MC and MD Default Signal Conditions 473 B-24Table B-8. 8XC196MC and MD Default Signal Conditions (Continued) 474 B-25Table B-9. 8XC196MH Default Signal Conditions 475 B-26Table B-9. 8XC196MH Default Signal Conditions (Continued) C-1 478 APPENDIX C REGISTERS552 GLOSSARY566 INDEX
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