D-20Instruction Set Quick Reference

Shift Register Instructions

Instruction

Description

 

 

BSL

BIT SHIFT LEFT

File

#B3:1

Control

R6:53

Bit Address

I:022/12

Length

5

Bit Shift Left

If the input conditions go from false-to-true, the BSL instruction

BSL

shifts the number of bits specified by Length (5) in File (B3),

 

starting at bit 16 (B3:1/0 = B3/16), to the left by one bit position.

Status Bits:

The source bit (I:022/12) shifts into the first bit position, B3:1/0

EN - Enable

(B3/16). The fifth bit, B3:1/4 (B3/20), is shifted into the UL bit of

DN - Done Bit

the control structure (R6:53).

ER - Error Bit

 

UL - Unload Bit

 

BSR

BIT SHIFT RIGHT

File

#B3:2

Control

R6:54

Bit Address

I:023/06

Length

3

Bit Shift Right

If the input conditions go from false-to-true, the BSR instruction

BSR

shifts the number of bits specified by Length (3) in File (B3),

 

starting with B3:2/0 (=B3/32), to the right by one bit position.

Status Bits:

The source bit (I:023/06) shifts into the third bit position B3/34.

EN - Enable

The first bit (B3/32) is shifted into the UL bit of the control

DN - Done Bit

element (R6:54).

ER - Error Bit

 

UL - Unload Bit

 

 

 

FFL

 

 

FIFO Load

When the input conditions go from false-to-true, the controller

 

 

 

 

 

 

 

 

FFL

loads N60:1 into the next available element in the FIFO file,

 

 

FIFO LOAD

 

 

 

 

 

#N60:3, as pointed to by R6:51. Each time the rung goes from

 

 

Source

N60:1

 

 

 

Status Bits:

false-to-true, the controller loads another element. When the

 

 

FIFO

#N60:3

EN - Enable Load

FIFO file (stack) is full, (64 words loaded), the DN bit is set.

 

 

Control

R6:51

DN - Done Bit

 

 

 

Length

64

 

 

 

EM - Empty Bit

See page F-8 for a description of prescan activities for

 

 

Position

0

 

 

 

this instruction.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIFO Unload

When the input conditions go from false-to-true, the controller

 

 

FFU

 

 

 

 

FIFO UNLOAD

 

FFU

unloads an element from #N60:3 into N60:2. Each time the rung

 

 

 

 

goes from false-to-true, the controller unloads another value.

 

 

FIFO

#N60:3

 

 

 

Status Bits:

All the data in file #N60:3 is shifted one position toward N60:3.

 

 

Dest

N60:2

EU - Enable Unload

When the file is empty, the EM bit is set.

 

 

Control

R6:51

DN - Done Bit

 

 

 

Length

64

 

 

 

EM - Empty Bit

See page F-8 for a description of prescan activities for this

 

 

Position

0

 

 

 

instruction.

 

 

 

 

 

 

 

 

 

 

 

 

 

Publication 1785-UM012D-EN-P - July 2005

Page 320
Image 320
Bradley Smoker PLC-5 user manual Shift Register Instructions, Bsl, Bsr, Ffl, Ffu