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Cisco MGX 8230 Edge Concentrator Installation and Configuration
Release 1.1.31, Part Number 78-11215-03 Rev. B0, May 2001
Chapter6 Card and Service Configuration
Circuit Emulation Service Module for T3 an d E3
Circuit Emulation Service Module for T3 and E3The main function of the Circuit Emulation Service Module (CESM) is to provide a constant bit rate
(CBR) service. The CESM co nverts da ta streams into CBR AAL1 cell s ac cording to the CES-IS
specifications of the ATM Forum for unstructured transport across an ATM network. Unstructured
transport means the CESM doe s not interpret or modify fra min g bi ts , s o a h ig h -sp ee d CES M cr eat es a
single data pipe The most common a ppl ica tion is le g ac y su ppo rt for di gi ti zed v oi ce from a P BX or vi de o
from a codec. Using circuit emulation, a company can expand its data communication network without
specific voice or video cards to m eet it s voi ce or t ele co nf er en ci ng r eq u ir eme nts.
The higher speed CESM uses a T3 or E3 line. The card set consists of an MGX-CESM-T3 or
MGX-CESM-E3 front card and either a BNC -2T3 or BNC-2E3 ba ck card. In this CESM a p pl ication,
only one line on the two-po rt back card is operational. F urthermore, it supports one logical port and one
logical connection (as a data pipe) on the line and runs at the full T3 or E3 rate. Although the typical
connection setup is the three- segment connection across an ATM network, th e CESM can support a DAX
connection. Up to 26 CESM ca rd s e ts c an operate in an MGX 8230 shelf .
Features
The MGX-CESM-T3 or MGX-CESM-E3 provide the following:
•Unstructured data transfer at 44.736 Mb ps (1189 980 cel ls per se cond) fo r T3 or 34.368 Mb ps (9140 5
cells per second) for E3
•Synchronous timing by either a local clock sourced on the PXM1 or loop timing (transmit clock
derived from receive clock on the line)
•1:1 redundancy is through a Y-cable
•Programmable egress buffer size (in the form of cell delay variation)
•Programmable cell delay variation tolerance (CDVT)
•Per VC queuing for the transmit and receive directions
•An idle code suppression option
•Bit count integrity when a lo s t A A L 1 cel l c ondition arises
•Alarm state definitions per G.704
•Trunk conditioning by way of framed AIS for T3 and unframed, alternating 1s and 0s for E3
•On-board bit error rate testing (BERT)
Cell Delay Treatment
You can configure a tolerable variation in the cell ar r ival tim e (C DVT) for the receive buffer. After an
underrun, the receiver places the con tents of the first cell to arrive in a receive buffer the n plays it out at
least one CDVT value later. The maxi mu m cell delay and CDVT (or ji tt er ) a r e:
•For T3
–
Cell delay of 4 msec
–
CDVT of 1.5 msec in increments o f 125 m i cr ose c o nds