Hardware Implementation Dependent 0 Register | Emerson PMPPC7448

Central Processing Unit:Processor Initialization

Hardware Implementation Dependent 0 Register

The Hardware Implementation Dependent 0 (HID0) register contains bits for CPU-specific features. Most of these bits are cleared on initial power-up of the PmPPC7448. Please refer to the MPC7450 RISC Microprocessor Family User’s Manual for more detailed descriptions of the HIDx registers. The following register map summarizes HID0 for the MPC7448 CPU:

Register 3-1:MPC7448 Hardware Implementation Dependent, HID0

0

4

5

6

7

8

9

10

11

12

13

14

15

reserved

TBE

R

STE

HBE

NAP

SLP

DPM

R

BHT

XAE

NHR

CLR

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

ICE

DCE

ILO

DLO

ICFI

DCFI

SPD

XBS

SGE

R

BTIC

LRST

FOL

BHT

NOP

NOP

CK

CK

EN

K

D

DST

TI

TBE: Time Base Enable—this bit must be set and the TBEN signal must be asserted to enable the time base and decrementer.

STE: Software Table Search Enable—after a TLB miss, one of the three TLB miss exceptions is taken so that software can search the page tables for the appropriate PTE.

0Hardware table search enabled

1Software table search enabled

HBE: High BATs Enable

0Additional 4 IBATs (4-7) and 4 DBATs (4-7) disabled

1Additional 4 IBATs (4-7) and 4 DBATs (4-7) enabled

NAP: Nap Mode Enable

0Nap mode disabled

1Nap mode enabled

SLP: Sleep Mode Enable

0Sleep mode disabled

1Sleep mode enabled

DPM: Dynamic Power Management Enable

0Dynamic power management is disabled

1Functional units enter low-power mode automatically if unit is idle

BHTCLR: Clear Branch History Table

0The MPC7448 clears this bit one cycle after it is set

1Setting this bit initializes all entries in BHT

10006757-02

PmPPC7448 User’s Manual

3-3

Image 41

Emerson PMPPC7448 Central Processing Unit Processor Initialization, Hardware Implementation Dependent 0 Register

Contents

PmPPC7448 PowerPC-Based Processor PMC Module Revision Level Principal Changes Date EMC Compliance Regulatory Agency Warnings & NoticesFCC Rules and Regulations Part Model Name/Number Manufacturer’s NameProduct Contents Contents Acronyms Blank Figures Viii Tables Blank Registers Xii Overview Components and Features Development Mezzanine Card DMC Overview Components and Features Functional Overview Overview Functional Overview Physical Memory MAP Overview Physical Memory Map EBFF,FFFF Hex Physical Access Address Mode Description See Overview Additional Information Type SpecificationAdditional Information Product Certification EMC UL Certification Terminology and Notation RoHS ComplianceTechnical References Device / Interface Document Document Device / Interface Intel StrataFlash Embedded Memory P30 Datasheet Blank Electrostatic Discharge SetupPMPPC7448 Circuit Board Width Depth Height top side Height bottom side C325 Setup PmPPC7448 Circuit Board PLD P14 Connectors 3LED Locations, Bottom LEDs Front Panel Front Panel Switch Reset PMPPC7448 Setup Setup PmPPC7448 Setup Environmental Considerations Power RequirementsRisk of damage to the board Environment Range Relative Humidity PMC Installing the Module Baseboard Setup TroubleshootingTroubleshooting Technical Support 8Serial Number and Product ID on Bottom Side Product Repair Setup Troubleshooting Central Processing Unit Category MPC7448 Key Features Processor Initialization Processor ResetRegister Default After Initialization Hex Hardware Implementation Dependent 0 Register Central Processing Unit Processor Initialization Central Processing Unit Processor Initialization Hardware Implementation Dependent 1 Register Exception Handling Central Processing Unit Exception Handling Priority Exception Post-Instruction Execution Machine State Register Central Processing Unit Exception ProcessingException Processing FE0 FE1 FP Exception Mode L1 Cache Central Processing Unit Cache MemoryCache Memory L2 Cache Central Processing Unit Cache Memory Boot Memory Configuration On-Card Memory ConfigurationJumper Function Options Default Configuration User Flash Nvram Allocation On-Card Memory Configuration On-Card SdramON-CARD Sdram Address Offset hex Name Bytes On-Card Memory Configuration Nvram AllocationWindow Size Blank XOR System Controller CPU Interface System Controller CPU InterfaceCPU Interface Registers Memory Interface Device Controller Interface System Controller Device Controller InterfaceInternal Sram System Controller Internal Idma Controller Timer/CounterDevice Control Registers Internal Idma Controller System Controller PCI Interface PCI Configuration SpacePCI Subsystem Device and Vendor ID Assignment PCI Read/Write Sdram Size PCI Interface Registers System Controller PCI Bus Control SignalsPCI BUS Control Signals Eready Ready PRESENT* Present PMC Connector Pinouts System Controller PMC Connector PinoutsPin P11 Signal P12 Signal P11 and P12 Pin Assignments P13 and P14 Pin Assignments Pin P13 Signal P14 Signal 6PMC Connector PMC Connector Doorbell Registers System Controller Doorbell RegistersOutbound Doorbells Inbound Doorbells Reset Watchdog TimerSystem Controller 66 MHz Bus Operation MHZ BUS Operation MV64460 Ethernet Registers Ethernet Interface Ethernet Connection P1 Ethernet Interface Ethernet AddressEthernet Address Ethernet Interface Ethernet Connection P1 Pin SignalCable may result in a disconnection Mini-B USB Pin Description RJ45 Pin Blank Reset Event Register RER Reset RegistersReset Command Register RCR Cpld SCL Cpld Reset Registers Interrupt Registers Cpld Interrupt Registers Interrupt Pending Register IPR Interrupt Enable Register IER Product ID Register PIR Cpld Product ID Register PIREready Register Erdy Revision Registers Board Configuration Registers Cpld Board Configuration RegistersHardware Version Register HVR PLD Version Register PVR Reserved Boot Blank Serial Input/Output BRGx Configuration RegisterMULTI-PROTOCOL Serial Controllers Mpsc Serial DMA Sdma Channels Serial Input/Output I2C Interface BRGx Tuning RegisterI2C Interface Connection Mini-USB Pin Description DB9 Pin Serial Input/Output I/O Connection Blank Operation Block DiagramReal-Time Clock Address Data Function/Range Real-Time Clock Clock OperationClock Operation Don’t care bit Blank DMC Circuit Board Development Mezzanine Card Serial Numbers Development Mezzanine Card DMC Circuit Board P1 Connector Pin Assignments Development Mezzanine Card ConnectorsConnectors OUT Dmcoe P2 EIA-232 Interface 3DMC P2 Mini-USB Connector P3 JTAG/COP Development Mezzanine Card PmPPC7448 to DMC JtagPMPPC7448 to DMC Jtag 6DMC P4 Jtag Chain Header P4 Jtag Chain Header DMC Jumpers JP1 Development Mezzanine Card DMC Jumpers JP1 DEBUG/STATUS Leds Jumper Setting RegisterDevelopment Mezzanine Card Debug/Status LEDs Installing the DMC Card Development Mezzanine Card DMC SetupDMC Setup DMC Location on PmPPC7448 Development Mezzanine Card Troubleshooting 10-14 Monitor COMMAND-LINE Features Basic Operation Power-up/Reset SequenceMonitor Basic Operation 2Power-up/Reset Sequence Flowchart Post Diagnostic Results Monitor Monitor Recovery and UpdatesMonitor Recovery and Updates Recovering the Monitor Updating the Monitor via Tftp PCI1 Restoring the PmPPC7448 Monitor Using the KatanaQP Verify that the checksum is correct Resetting Environment Variables Monitor Command Reference Monitor Accessing the Console Over EthernetAccessing the Console Over Ethernet Boot Commands Monitor Boot Commands Bootm BootelfBootp Bootv Memory Commands Monitor Memory Commands Find Definition mm .b, .w, .l address Flash Commands Monitor Flash CommandsErase Flinfo EEPROM/I2C Commands Monitor EEPROM/I2C CommandsProtect Eeprom Iloop Icrc32Imd Imm Test Commands Monitor Environment Parameter CommandsEnvironment Parameter Commands Other Commands Monitor Other Commands Date Crc32Echo Enumpci Iminfo HelpIsdram Loop Run PciPing Environment Variables Monitor Environment Variables Bootfile Variable Description Download Formats Monitor TroubleshootingBinary Motorola S-Record 11-26 CPSB AcronymsGbE PrPMC RMA Index Contents, table Cpld registers -1 to 11-17 Index UL certifications Blank 10006757-02 E R S O N. C O N S I D E R I T S O L V E D