Emerson PMPPC7448 user manual Central Processing Unit:Processor Initialization

Central Processing Unit:Processor Initialization

Hardware Implementation Dependent 0 Register

The Hardware Implementation Dependent 0 (HID0) register contains bits for CPU-specific features. Most of these bits are cleared on initial power-up of the PmPPC7448. Please refer to the MPC7450 RISC Microprocessor Family User’s Manual for more detailed descriptions of the HIDx registers. The following register map summarizes HID0 for the MPC7448 CPU:

Register 3-1:MPC7448 Hardware Implementation Dependent, HID0

0				4	5	6	7	8	9	10	11	12	13	14	15
		reserved			TBE	R	STE	HBE	NAP	SLP	DPM	R	BHT	XAE	NHR
													CLR
16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31
ICE	DCE	ILO	DLO	ICFI	DCFI	SPD	XBS	SGE	R	BTIC	LRST	FOL	BHT	NOP	NOP
		CK	CK				EN				K	D		DST	TI

TBE: Time Base Enable—this bit must be set and the TBEN signal must be asserted to enable the time base and decrementer.

STE: Software Table Search Enable—after a TLB miss, one of the three TLB miss exceptions is taken so that software can search the page tables for the appropriate PTE.

0Hardware table search enabled

1Software table search enabled

HBE: High BATs Enable

0Additional 4 IBATs (4-7) and 4 DBATs (4-7) disabled

1Additional 4 IBATs (4-7) and 4 DBATs (4-7) enabled

NAP: Nap Mode Enable

0Nap mode disabled

1Nap mode enabled

SLP: Sleep Mode Enable

0Sleep mode disabled

1Sleep mode enabled

DPM: Dynamic Power Management Enable

0Dynamic power management is disabled

1Functional units enter low-power mode automatically if unit is idle

BHTCLR: Clear Branch History Table

0The MPC7448 clears this bit one cycle after it is set

1Setting this bit initializes all entries in BHT

10006757-02 PmPPC7448 User’s Manual

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