Cpld, Reset Registers, Reset Event Register RER | Emerson PMPPC7448

Section 7

CPLD

This chapter lists the registers implemented by the complex programmable logic device (CPLD).

RESET REGISTERS

The reset signals are routed to and distributed by the CPLD. To support this functionality, the CPLD includes two registers; one indicates the reason for the last reset, and the other forces one of several types of reset.

Reset Event Register (RER)

This read-only register contains the cause of the latest reset.

Register 7-1:Reset Event Register (RER) at 0xf820,0000

7

6

5

4

3

2

1

0

InitAct

SW

WD

COPS

COPH

R

PCIO

FP

InitAct: Initialization Active

Set to 1 when the MV64460 InitAct pin does not go inactive after reset.

SW: Software

Set to 1 when the last reset was caused by a write to the Reset Command register.

WD: Watchdog

Set to 1 when a reset was caused by the expiration of the MV64460 watchdog timer.

COPS: Soft Reset

Set to 1 when a COP header soft reset (SRESET) has occurred.

COPH: Hard Reset

Set to 1 when a COP header hard reset (HRESET) has occurred.

R:Reserved (default is 00)

PCIO: PCI O

Set to 1 when a PMC PCI reset (RST* signal) has occurred.

FP: Front Panel

Set to 1 when the front panel switch caused a reset.

Reset Command Register (RCR)

The Reset Command register forces one of several types of resets, as shown below. A reset sequence is initiated by writing a one to a valid bit, then the bit is automatically cleared.

10006757-02

PmPPC7448 User’s Manual

7-1

Image 73

Emerson PMPPC7448 user manual Cpld, Reset Registers, Reset Event Register RER, Reset Command Register RCR

Contents

PmPPC7448 PowerPC-Based Processor PMC Module Revision Level Principal Changes Date FCC Rules and Regulations Part Regulatory Agency Warnings & NoticesEMC Compliance Product Manufacturer’s NameModel Name/Number Contents Contents Acronyms Blank Figures Viii Tables Blank Registers Xii Overview Components and Features Development Mezzanine Card DMC Overview Components and Features Functional Overview Overview Functional Overview Physical Memory MAP Overview Physical Memory Map EBFF,FFFF Hex Physical Access Address Mode Description See Overview Additional Information Type SpecificationAdditional Information Product Certification EMC UL Certification Terminology and Notation RoHS ComplianceTechnical References Device / Interface Document Document Device / Interface Intel StrataFlash Embedded Memory P30 Datasheet Blank Electrostatic Discharge SetupPMPPC7448 Circuit Board Width Depth Height top side Height bottom side C325 Setup PmPPC7448 Circuit Board PLD P14 Connectors 3LED Locations, Bottom LEDs Front Panel Front Panel Switch Reset PMPPC7448 Setup Setup PmPPC7448 Setup Environmental Considerations Power RequirementsRisk of damage to the board Environment Range Relative Humidity PMC Installing the Module Troubleshooting Setup TroubleshootingBaseboard Technical Support 8Serial Number and Product ID on Bottom Side Product Repair Setup Troubleshooting Central Processing Unit Category MPC7448 Key Features Register Default After Initialization Hex Processor ResetProcessor Initialization Hardware Implementation Dependent 0 Register Central Processing Unit Processor Initialization Central Processing Unit Processor Initialization Hardware Implementation Dependent 1 Register Exception Handling Central Processing Unit Exception Handling Priority Exception Post-Instruction Execution Exception Processing Central Processing Unit Exception ProcessingMachine State Register FE0 FE1 FP Exception Mode Cache Memory Central Processing Unit Cache MemoryL1 Cache L2 Cache Central Processing Unit Cache Memory Boot Memory Configuration On-Card Memory ConfigurationJumper Function Options Default Configuration User Flash ON-CARD Sdram On-Card Memory Configuration On-Card SdramNvram Allocation Window Size On-Card Memory Configuration Nvram AllocationAddress Offset hex Name Bytes Blank XOR System Controller CPU Interface System Controller CPU InterfaceCPU Interface Registers Memory Interface Internal Sram System Controller Device Controller InterfaceDevice Controller Interface System Controller Internal Idma Controller Timer/CounterDevice Control Registers Internal Idma Controller System Controller PCI Interface PCI Configuration SpacePCI Subsystem Device and Vendor ID Assignment PCI Read/Write Sdram Size PCI BUS Control Signals System Controller PCI Bus Control SignalsPCI Interface Registers Eready Ready PRESENT* Present PMC Connector Pinouts System Controller PMC Connector PinoutsPin P11 Signal P12 Signal P11 and P12 Pin Assignments P13 and P14 Pin Assignments Pin P13 Signal P14 Signal 6PMC Connector PMC Connector Doorbell Registers System Controller Doorbell RegistersOutbound Doorbells Inbound Doorbells Reset Watchdog TimerSystem Controller 66 MHz Bus Operation MHZ BUS Operation MV64460 Ethernet Registers Ethernet Interface Ethernet Address Ethernet Interface Ethernet AddressEthernet Connection P1 Ethernet Interface Ethernet Connection P1 Pin SignalCable may result in a disconnection Mini-B USB Pin Description RJ45 Pin Blank Reset Event Register RER Reset RegistersReset Command Register RCR Cpld SCL Cpld Reset Registers Interrupt Registers Cpld Interrupt Registers Interrupt Pending Register IPR Interrupt Enable Register IER Product ID Register PIR Cpld Product ID Register PIREready Register Erdy Revision Registers Board Configuration Registers Cpld Board Configuration RegistersHardware Version Register HVR PLD Version Register PVR Reserved Boot Blank Serial Input/Output BRGx Configuration RegisterMULTI-PROTOCOL Serial Controllers Mpsc Serial DMA Sdma Channels Serial Input/Output I2C Interface BRGx Tuning RegisterI2C Interface Connection Mini-USB Pin Description DB9 Pin Serial Input/Output I/O Connection Blank Real-Time Clock Block DiagramOperation Clock Operation Real-Time Clock Clock OperationAddress Data Function/Range Don’t care bit Blank DMC Circuit Board Development Mezzanine Card Serial Numbers Development Mezzanine Card DMC Circuit Board Connectors Development Mezzanine Card ConnectorsP1 Connector Pin Assignments OUT Dmcoe P2 EIA-232 Interface 3DMC P2 Mini-USB Connector PMPPC7448 to DMC Jtag Development Mezzanine Card PmPPC7448 to DMC JtagP3 JTAG/COP 6DMC P4 Jtag Chain Header P4 Jtag Chain Header DMC Jumpers JP1 Development Mezzanine Card DMC Jumpers JP1 Development Mezzanine Card Debug/Status LEDs Jumper Setting RegisterDEBUG/STATUS Leds DMC Setup Development Mezzanine Card DMC SetupInstalling the DMC Card DMC Location on PmPPC7448 Development Mezzanine Card Troubleshooting 10-14 Monitor COMMAND-LINE Features Monitor Basic Operation Power-up/Reset SequenceBasic Operation 2Power-up/Reset Sequence Flowchart Post Diagnostic Results Monitor Monitor Recovery and UpdatesMonitor Recovery and Updates Recovering the Monitor Updating the Monitor via Tftp PCI1 Restoring the PmPPC7448 Monitor Using the KatanaQP Verify that the checksum is correct Resetting Environment Variables Accessing the Console Over Ethernet Monitor Accessing the Console Over EthernetMonitor Command Reference Boot Commands Monitor Boot Commands Bootm BootelfBootp Bootv Memory Commands Monitor Memory Commands Find Definition mm .b, .w, .l address Flash Commands Monitor Flash CommandsErase Flinfo EEPROM/I2C Commands Monitor EEPROM/I2C CommandsProtect Eeprom Iloop Icrc32Imd Imm Environment Parameter Commands Monitor Environment Parameter CommandsTest Commands Other Commands Monitor Other Commands Date Crc32Echo Enumpci Iminfo HelpIsdram Loop Ping PciRun Environment Variables Monitor Environment Variables Bootfile Variable Description Download Formats Monitor TroubleshootingBinary Motorola S-Record 11-26 CPSB AcronymsGbE PrPMC RMA Index Contents, table Cpld registers -1 to 11-17 Index UL certifications Blank 10006757-02 E R S O N. C O N S I D E R I T S O L V E D