Section 6
Ethernet Interface
The PmPPC7448 provides three independent full duplex Ethernet ports. Using the Marvell MV64460, these ports are configured to one 10/100 Mbps Media Independent Interface (MII) and two 10/100/1000 Mbps Gigabit MII (GMII). The two gigabit Ethernet ports (ports 0 and 1) are routed through PMC connector P14. The 10/100 Mbps Ethernet port (port 2) is routed to the front panel
Note: Since GbE ports 0 and 1 are routed through the PHYs directly to connector P14, magnetics are required on the Rear Transition Module (RTM) or baseboard.
Some additional Ethernet features on the MV64460 include:
•IEEE 802.3 compliant MAC layer function
•10/100/1000 megabit operation — half and full duplex are automatically mapped out through the PHY
•IEEE 802.3x
•Internal and external loop back modes
•Short frame transmission (less than 64 bytes) zero padding and long frame transmission (limited only by external memory size)
The Micrel KSZ8721CL
•Compliance with IEEE 802.3 standards
•Compliance with PICMG 2.15 standards
•Low power consumption; less than 340 mW
•IEEE 1149.1 (JTAG) boundary scan chain support
Note: Proprietary information on the Micrel and Broadcom Ethernet transceiver devices is not available in this user’s manual. Please refer to the Micrel web site at http://www.micrel.com or the Broadcom web site at http://www.broadcom.com for available documentation.
MV64460 ETHERNET REGISTERS
The MV64460 is capable of implementing three 10/100/1000 Ethernet controllers. These controllers interface with the PHY via MII or GMII interface.
The Serial Management Interface (SMI) unit continuously queries the PHY devices for their link status. The PHY addresses for the link query operation are programmable per port in the PHY_Address register.
PmPPC7448 User’s Manual |
