Monitor, COMMAND-LINE Features | Emerson PMPPC7448 specs

Section 11

Monitor

The PmPPC7448 monitor is based on the Universal Boot (U-Boot) program, available under the GNU General Public License (GPL). For instructions on how to obtain the source code for this GPL program, please visit http://www.emersonembeddedcomputing.com, send an e- mail to support@artesyncp.com, or call Emerson at 1-800-327-1251.

This chapter describes the monitor’s basic features, operation, and configuration sequences. This chapter also serves as a reference for the monitor commands and func- tions.

COMMAND-LINE FEATURES

The PmPPC7448 monitor uses a command-line interface with the following features:

Auto-Repeat:After entering a command, you can re-execute it simply by pressing the ENTER or RETURN key.

TFTP Boot: You can use the TFTP protocol to load application images via Ethernet into the

PmPPC7448’s memory.

Auto-Boot:You can store specific boot commands in the environment to be executed automatically after reset.

Flash Programming: You can write application images into Flash via the U-Boot command line. One megabyte at the base of Flash is reserved for the monitor.

At power-up or after a reset, the monitor runs diagnostics and reports the results in the start-up display, see Fig. 11-1. During the power-up sequence, the monitor configures the board according to the environment variables (see “Environment Variables” on

page 11-22)and settings in the Board Configuration registers (see “Board Configuration Registers” on page 7-6). If the configuration indicates that autoboot is enabled, the moni- tor attempts to load the application from the specified device. If the monitor is not config- ured for autoboot or a failure occurs during power-up, the monitor enters normal command-line mode.

10006757-02

PmPPC7448 User’s Manual

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Emerson PMPPC7448 user manual Monitor, COMMAND-LINE Features

Contents

PmPPC7448 PowerPC-Based Processor PMC Module Revision Level Principal Changes Date FCC Rules and Regulations Part Regulatory Agency Warnings & NoticesEMC Compliance Product Manufacturer’s NameModel Name/Number Contents Contents Acronyms Blank Figures Viii Tables Blank Registers Xii Overview Components and Features Development Mezzanine Card DMC Overview Components and Features Functional Overview Overview Functional Overview Physical Memory MAP Overview Physical Memory Map EBFF,FFFF Hex Physical Access Address Mode Description See Product Certification Type SpecificationOverview Additional Information Additional Information EMC UL Certification Device / Interface Document RoHS ComplianceTerminology and Notation Technical References Document Device / Interface Intel StrataFlash Embedded Memory P30 Datasheet Blank Width Depth Height top side Height bottom side SetupElectrostatic Discharge PMPPC7448 Circuit Board C325 Setup PmPPC7448 Circuit Board PLD P14 Connectors 3LED Locations, Bottom LEDs Front Panel Front Panel Switch Reset PMPPC7448 Setup Setup PmPPC7448 Setup Environment Range Relative Humidity Power RequirementsEnvironmental Considerations Risk of damage to the board PMC Installing the Module Troubleshooting Setup TroubleshootingBaseboard Technical Support 8Serial Number and Product ID on Bottom Side Product Repair Setup Troubleshooting Central Processing Unit Category MPC7448 Key Features Register Default After Initialization Hex Processor ResetProcessor Initialization Hardware Implementation Dependent 0 Register Central Processing Unit Processor Initialization Central Processing Unit Processor Initialization Hardware Implementation Dependent 1 Register Exception Handling Central Processing Unit Exception Handling Priority Exception Post-Instruction Execution Exception Processing Central Processing Unit Exception ProcessingMachine State Register FE0 FE1 FP Exception Mode Cache Memory Central Processing Unit Cache MemoryL1 Cache L2 Cache Central Processing Unit Cache Memory User Flash On-Card Memory ConfigurationBoot Memory Configuration Jumper Function Options Default Configuration ON-CARD Sdram On-Card Memory Configuration On-Card SdramNvram Allocation Window Size On-Card Memory Configuration Nvram AllocationAddress Offset hex Name Bytes Blank XOR System Controller Memory Interface System Controller CPU InterfaceCPU Interface CPU Interface Registers Internal Sram System Controller Device Controller InterfaceDevice Controller Interface Internal Idma Controller Timer/CounterSystem Controller Internal Idma Controller Device Control Registers PCI Read/Write PCI Configuration SpaceSystem Controller PCI Interface PCI Subsystem Device and Vendor ID Assignment Sdram Size PCI BUS Control Signals System Controller PCI Bus Control SignalsPCI Interface Registers Eready Ready PRESENT* Present P11 and P12 Pin Assignments System Controller PMC Connector PinoutsPMC Connector Pinouts Pin P11 Signal P12 Signal P13 and P14 Pin Assignments Pin P13 Signal P14 Signal 6PMC Connector PMC Connector Inbound Doorbells System Controller Doorbell RegistersDoorbell Registers Outbound Doorbells MHZ BUS Operation Watchdog TimerReset System Controller 66 MHz Bus Operation MV64460 Ethernet Registers Ethernet Interface Ethernet Address Ethernet Interface Ethernet AddressEthernet Connection P1 Mini-B USB Pin Description RJ45 Pin Pin SignalEthernet Interface Ethernet Connection P1 Cable may result in a disconnection Blank Cpld Reset RegistersReset Event Register RER Reset Command Register RCR SCL Cpld Reset Registers Interrupt Registers Cpld Interrupt Registers Interrupt Pending Register IPR Interrupt Enable Register IER Revision Registers Cpld Product ID Register PIRProduct ID Register PIR Eready Register Erdy PLD Version Register PVR Cpld Board Configuration RegistersBoard Configuration Registers Hardware Version Register HVR Reserved Boot Blank Serial DMA Sdma Channels BRGx Configuration RegisterSerial Input/Output MULTI-PROTOCOL Serial Controllers Mpsc Connection BRGx Tuning RegisterSerial Input/Output I2C Interface I2C Interface Mini-USB Pin Description DB9 Pin Serial Input/Output I/O Connection Blank Real-Time Clock Block DiagramOperation Clock Operation Real-Time Clock Clock OperationAddress Data Function/Range Don’t care bit Blank DMC Circuit Board Development Mezzanine Card Serial Numbers Development Mezzanine Card DMC Circuit Board Connectors Development Mezzanine Card ConnectorsP1 Connector Pin Assignments OUT Dmcoe P2 EIA-232 Interface 3DMC P2 Mini-USB Connector PMPPC7448 to DMC Jtag Development Mezzanine Card PmPPC7448 to DMC JtagP3 JTAG/COP 6DMC P4 Jtag Chain Header P4 Jtag Chain Header DMC Jumpers JP1 Development Mezzanine Card DMC Jumpers JP1 Development Mezzanine Card Debug/Status LEDs Jumper Setting RegisterDEBUG/STATUS Leds DMC Setup Development Mezzanine Card DMC SetupInstalling the DMC Card DMC Location on PmPPC7448 Development Mezzanine Card Troubleshooting 10-14 Monitor COMMAND-LINE Features Monitor Basic Operation Power-up/Reset SequenceBasic Operation 2Power-up/Reset Sequence Flowchart Recovering the Monitor Monitor Monitor Recovery and UpdatesPost Diagnostic Results Monitor Recovery and Updates Updating the Monitor via Tftp PCI1 Restoring the PmPPC7448 Monitor Using the KatanaQP Verify that the checksum is correct Resetting Environment Variables Accessing the Console Over Ethernet Monitor Accessing the Console Over EthernetMonitor Command Reference Boot Commands Monitor Boot Commands Bootv BootelfBootm Bootp Memory Commands Monitor Memory Commands Find Definition mm .b, .w, .l address Flinfo Monitor Flash CommandsFlash Commands Erase Eeprom Monitor EEPROM/I2C CommandsEEPROM/I2C Commands Protect Imm Icrc32Iloop Imd Environment Parameter Commands Monitor Environment Parameter CommandsTest Commands Other Commands Monitor Other Commands Enumpci Crc32Date Echo Loop HelpIminfo Isdram Ping PciRun Environment Variables Monitor Environment Variables Bootfile Variable Description Motorola S-Record Monitor TroubleshootingDownload Formats Binary 11-26 PrPMC AcronymsCPSB GbE RMA Index Contents, table Cpld registers -1 to 11-17 Index UL certifications Blank 10006757-02 E R S O N. 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