Emerson PMPPC7448 user manual Serial Input/Output, MULTI-PROTOCOL Serial Controllers Mpsc

Section 8

Serial Input/Output

The PmPPC7448 has two EIA-232 serial ports. These ports operate between 9600 and 115,200 baud. Software selects the speed and these settings are stored in non-volatile memory. Serial port one is always routed to the Development Mezzanine Card (DMC) serial connector as 12 volts; build options include connections to the front panel serial connector, or the P14 connector. When routed to P14, there is the option of either EIA-232 or TTL sig- naling levels. Port two is routed to P14 with the same options. The Marvell MV64460 sys- tem controller provides the communication ports for the PmPPC7448. For more detailed information on the MV64460, reference the web site http://www.marvell.com.

MULTI-PROTOCOL SERIAL CONTROLLERS (MPSC)

The MV64460 has two MPSCs with each channel supporting HDLC, BISYNC, UART, or Trans- parent protocols.

Signals Routing: The two MPSCs can be routed to serial port 0 and serial port 1, or not connected. These are defined in the Main Routing register (MRR).

MPSCx Main Configuration Registers:

Each MPSC has an MPSC Main Configuration register (MMCRx) for port 0 and port 1. The MMCRx is a 64-bit register that configures common MPSC features and is protocol indepen- dent. Each MMCRx consists of two 32-bit registers, MMCRLx (low) and MMCRHx (high).

SERIAL DMA (SDMA) CHANNELS

Two of the SDMA channels support data movement between the MPSCs and memory buff- ers on the MV64460. Each channel consists of a DMA engine for receiving and one for trans- mitting. The SDMA uses a linked chain of descriptors and buffers to reduce CPU overhead.

PROGRAMMABLE BAUD RATE

The MV64460 has two programmable baud rate generators (BRG); each with five clock inputs: BClkIn, TClk, SCLK, TSCLK, and CLKSel.

BRGx Configuration Register

When a BRG is enabled, it loads the Count Down Value (CDV) from the BRG configuration register into its count down counter. When the counter expires (reaches zero), the BRG clock output (BCLK) is toggled and the counter reloads.

Note: The EIA-232C specification defines a maximum rate of 20,000 bits per second over a typical 50-foot cable (2,500 picofarads maximum load capacitance). Higher baud rates are possible, but depend specifically upon the application, cable length, and overall signal quality.

10006757-02 PmPPC7448 User’s Manual

8-1