Out | Emerson PMPPC7448 specification

Development Mezzanine Card:Connectors


	Pin:					Signal:											Pin:						Signal:
	Pin:					Signal:											Pin:						Signal:
	19					LA7											20						LA6

	21					LA5											22						LA4

	23					LA3											24						LA2

	25					BADDR2											26						BADDR1

	27					BADDR0											28						AD7

	29					AD6											30						AD5

	31					AD4											32						AD3

	33					AD2											34						AD1

	35					AD0											36						FILT_TX

	37					FILT_RX											38						GND

	39					CPU_VIO											40						3.3 V
						(DMC JTAG)

	41					3.3 V											42						MPC7448_TCK

	43					GND											44						Not connected
	45					Not connected											46						Not connected
	47					Not connected											48						Not connected
	49					Not connected											50						Not connected
	51					DMC_JP1											52						DMC_BOOT_SRC

	53					DMC_JP3											54						DMC_JP4

	55					LED1*											56						LED2*

	57					LED3*											58						LED4*

	59					MPC7448_TDO											60						MPC7448_TDI

	61					DEBUG_TRST*											62						MPC7448_TMS

	63					DEBUG_SRESET*											64						DEBUG_HRESET*

	65					MPC7448_CKSTP											66						Not connected
						_OUT
	67					Not connected											68						Not connected
	69					Not connected											70						Not connected
	71					Not connected											72						CPLD_TDI
	73					CPLD_TMS											74						CPLD_TDO
						GND/DMC_PD11
	75					GND/DMC_PD11											76						Not connected
	77					Not connected											78						GND
	79					Not connected											80						3.3 V

1.When pin 75 is grounded, this notifies the PmPPC7448 that a DMC module is attached—presence detect (PD).

3.3V: 3.3 V is the power supply to the DMC (analog).

CPLD_TCK: PLD Test Clock is an input to DMC and part of the PLD JTAG interface.

DMC_CS*: Chip Select for DMC Flash is an input to DMC.

10-4

PmPPC7448 User’s Manual

10006757-02

Image 92

Emerson PMPPC7448 user manual Out

Contents

PmPPC7448 PowerPC-Based Processor PMC Module Revision Level Principal Changes Date EMC Compliance Regulatory Agency Warnings & NoticesFCC Rules and Regulations Part Model Name/Number Manufacturer’s NameProduct Contents Contents Acronyms Blank Figures Viii Tables Blank Registers Xii Components and Features Overview Overview Components and Features Development Mezzanine Card DMC Overview Functional Overview Functional Overview Overview Physical Memory Map Physical Memory MAP Hex Physical Access Address Mode Description See EBFF,FFFF Type Specification Overview Additional InformationAdditional Information Product Certification UL Certification EMC RoHS Compliance Terminology and NotationTechnical References Device / Interface Document Intel StrataFlash Embedded Memory P30 Datasheet Document Device / Interface Blank Setup Electrostatic DischargePMPPC7448 Circuit Board Width Depth Height top side Height bottom side Setup PmPPC7448 Circuit Board C325 PLD Connectors P14 LEDs 3LED Locations, Bottom Front Panel Front Panel Reset Switch Setup PmPPC7448 Setup PMPPC7448 Setup Power Requirements Environmental ConsiderationsRisk of damage to the board Environment Range Relative Humidity Installing the Module PMC Baseboard Setup TroubleshootingTroubleshooting Technical Support Product Repair 8Serial Number and Product ID on Bottom Side Setup Troubleshooting Category MPC7448 Key Features Central Processing Unit Processor Initialization Processor ResetRegister Default After Initialization Hex Central Processing Unit Processor Initialization Hardware Implementation Dependent 0 Register Central Processing Unit Processor Initialization Hardware Implementation Dependent 1 Register Central Processing Unit Exception Handling Exception Handling Post-Instruction Execution Priority Exception Machine State Register Central Processing Unit Exception ProcessingException Processing FE0 FE1 FP Exception Mode L1 Cache Central Processing Unit Cache MemoryCache Memory L2 Cache Central Processing Unit Cache Memory On-Card Memory Configuration Boot Memory ConfigurationJumper Function Options Default Configuration User Flash Nvram Allocation On-Card Memory Configuration On-Card SdramON-CARD Sdram Address Offset hex Name Bytes On-Card Memory Configuration Nvram AllocationWindow Size Blank System Controller XOR System Controller CPU Interface CPU InterfaceCPU Interface Registers Memory Interface Device Controller Interface System Controller Device Controller InterfaceInternal Sram Timer/Counter System Controller Internal Idma ControllerDevice Control Registers Internal Idma Controller PCI Configuration Space System Controller PCI InterfacePCI Subsystem Device and Vendor ID Assignment PCI Read/Write Sdram Size PCI Interface Registers System Controller PCI Bus Control SignalsPCI BUS Control Signals Eready Ready PRESENT* Present System Controller PMC Connector Pinouts PMC Connector PinoutsPin P11 Signal P12 Signal P11 and P12 Pin Assignments Pin P13 Signal P14 Signal P13 and P14 Pin Assignments PMC Connector 6PMC Connector System Controller Doorbell Registers Doorbell RegistersOutbound Doorbells Inbound Doorbells Watchdog Timer ResetSystem Controller 66 MHz Bus Operation MHZ BUS Operation Ethernet Interface MV64460 Ethernet Registers Ethernet Connection P1 Ethernet Interface Ethernet AddressEthernet Address Pin Signal Ethernet Interface Ethernet Connection P1Cable may result in a disconnection Mini-B USB Pin Description RJ45 Pin Blank Reset Registers Reset Event Register RERReset Command Register RCR Cpld Cpld Reset Registers SCL Cpld Interrupt Registers Interrupt Registers Interrupt Enable Register IER Interrupt Pending Register IPR Cpld Product ID Register PIR Product ID Register PIREready Register Erdy Revision Registers Cpld Board Configuration Registers Board Configuration RegistersHardware Version Register HVR PLD Version Register PVR Reserved Boot Blank BRGx Configuration Register Serial Input/OutputMULTI-PROTOCOL Serial Controllers Mpsc Serial DMA Sdma Channels BRGx Tuning Register Serial Input/Output I2C InterfaceI2C Interface Connection Serial Input/Output I/O Connection Mini-USB Pin Description DB9 Pin Blank Operation Block DiagramReal-Time Clock Address Data Function/Range Real-Time Clock Clock OperationClock Operation Don’t care bit Blank Development Mezzanine Card DMC Circuit Board Development Mezzanine Card DMC Circuit Board Serial Numbers P1 Connector Pin Assignments Development Mezzanine Card ConnectorsConnectors OUT Dmcoe 3DMC P2 Mini-USB Connector P2 EIA-232 Interface P3 JTAG/COP Development Mezzanine Card PmPPC7448 to DMC JtagPMPPC7448 to DMC Jtag P4 Jtag Chain Header 6DMC P4 Jtag Chain Header Development Mezzanine Card DMC Jumpers JP1 DMC Jumpers JP1 DEBUG/STATUS Leds Jumper Setting RegisterDevelopment Mezzanine Card Debug/Status LEDs Installing the DMC Card Development Mezzanine Card DMC SetupDMC Setup DMC Location on PmPPC7448 Development Mezzanine Card Troubleshooting 10-14 COMMAND-LINE Features Monitor Basic Operation Power-up/Reset SequenceMonitor Basic Operation 2Power-up/Reset Sequence Flowchart Monitor Monitor Recovery and Updates Post Diagnostic ResultsMonitor Recovery and Updates Recovering the Monitor Updating the Monitor via Tftp Restoring the PmPPC7448 Monitor Using the KatanaQP PCI1 Resetting Environment Variables Verify that the checksum is correct Monitor Command Reference Monitor Accessing the Console Over EthernetAccessing the Console Over Ethernet Monitor Boot Commands Boot Commands Bootelf BootmBootp Bootv Monitor Memory Commands Memory Commands Find Definition mm .b, .w, .l address Monitor Flash Commands Flash CommandsErase Flinfo Monitor EEPROM/I2C Commands EEPROM/I2C CommandsProtect Eeprom Icrc32 IloopImd Imm Test Commands Monitor Environment Parameter CommandsEnvironment Parameter Commands Monitor Other Commands Other Commands Crc32 DateEcho Enumpci Help IminfoIsdram Loop Run PciPing Monitor Environment Variables Environment Variables Bootfile Variable Description Monitor Troubleshooting Download FormatsBinary Motorola S-Record 11-26 Acronyms CPSBGbE PrPMC RMA Contents, table Cpld registers -1 to Index Index 11-17 UL certifications Blank 10006757-02 E R S O N. C O N S I D E R I T S O L V E D