Serial Input/Output I2C Interface, Connection | Emerson PMPPC7448

Table 8-2

Serial Input/Output: I2C Interface

BRGx Tuning Register

A baud tuning mechanism adjusts the generated clock rate to the receive clock rate. When baud tuning is enabled, the baud tuning mechanism monitors for a start bit (for example high-to-low transition). Once the start bit is found, the baud tuning machine measures the bit length by counting up until the next Low-to-High transition. Then the count-up value of the BRG is loaded into the Count Up Value (CUV) register and a maskable interrupt is gener- ated signaling the CPU that the bit length value is available. Finally, the CPU reads the value from the CUV and adjusts the CDV to the requested value.

I2C INTERFACE

The MV64460 has full I2C interface support, acting as both a master generating read/write requests and as a slave responding to read/write requests. The I2C port consists of two open drain signals—serial clock (SCL) and serial data/address (SDA).

Note: Marvell documentation refers to this as the Two-Wire Serial Interface (TWSI).

An I2C serial configuration ROM is connected to the MV64460’s I2C interface, and is dis- abled by default. Emerson uses the addresses in Table 8-1for I2C devices.

Table 8-1:I2C Device Addresses

Device (reference designator):	Hex Address:
64460 I2C (U33)	0xA4
NVRAM I2C (U34)	0xA6
RTC (U36)	0xD0

SO-DIMM I2C (U3)	0xAE

I/O CONNECTION

Specific PmPPC7448 configurations provide a standard EIA-232 serial I/O port; P2 is a mini-

USB connector available at the front panel. See below. The cable wiring assign- ments are in Table 8-3.

Figure 8-1:Front Panel Serial Port Connector (P2)

Pin 1

8-2

PmPPC7448 User’s Manual

10006757-02

Image 82

Emerson PMPPC7448 user manual Serial Input/Output I2C Interface, BRGx Tuning Register, Connection

Contents

PmPPC7448 PowerPC-Based Processor PMC Module Revision Level Principal Changes Date FCC Rules and Regulations Part Regulatory Agency Warnings & NoticesEMC Compliance Product Manufacturer’s NameModel Name/Number Contents Contents Acronyms Blank Figures Viii Tables Blank Registers Xii Components and Features Overview Overview Components and Features Development Mezzanine Card DMC Overview Functional Overview Functional Overview Overview Physical Memory Map Physical Memory MAP Hex Physical Access Address Mode Description See EBFF,FFFF Additional Information Type SpecificationOverview Additional Information Product Certification UL Certification EMC Technical References RoHS ComplianceTerminology and Notation Device / Interface Document Intel StrataFlash Embedded Memory P30 Datasheet Document Device / Interface Blank PMPPC7448 Circuit Board SetupElectrostatic Discharge Width Depth Height top side Height bottom side Setup PmPPC7448 Circuit Board C325 PLD Connectors P14 LEDs 3LED Locations, Bottom Front Panel Front Panel Reset Switch Setup PmPPC7448 Setup PMPPC7448 Setup Risk of damage to the board Power RequirementsEnvironmental Considerations Environment Range Relative Humidity Installing the Module PMC Troubleshooting Setup TroubleshootingBaseboard Technical Support Product Repair 8Serial Number and Product ID on Bottom Side Setup Troubleshooting Category MPC7448 Key Features Central Processing Unit Register Default After Initialization Hex Processor ResetProcessor Initialization Central Processing Unit Processor Initialization Hardware Implementation Dependent 0 Register Central Processing Unit Processor Initialization Hardware Implementation Dependent 1 Register Central Processing Unit Exception Handling Exception Handling Post-Instruction Execution Priority Exception Exception Processing Central Processing Unit Exception ProcessingMachine State Register FE0 FE1 FP Exception Mode Cache Memory Central Processing Unit Cache MemoryL1 Cache L2 Cache Central Processing Unit Cache Memory Jumper Function Options Default Configuration On-Card Memory ConfigurationBoot Memory Configuration User Flash ON-CARD Sdram On-Card Memory Configuration On-Card SdramNvram Allocation Window Size On-Card Memory Configuration Nvram AllocationAddress Offset hex Name Bytes Blank System Controller XOR CPU Interface Registers System Controller CPU InterfaceCPU Interface Memory Interface Internal Sram System Controller Device Controller InterfaceDevice Controller Interface Device Control Registers Timer/CounterSystem Controller Internal Idma Controller Internal Idma Controller PCI Subsystem Device and Vendor ID Assignment PCI Configuration SpaceSystem Controller PCI Interface PCI Read/Write Sdram Size PCI BUS Control Signals System Controller PCI Bus Control SignalsPCI Interface Registers Eready Ready PRESENT* Present Pin P11 Signal P12 Signal System Controller PMC Connector PinoutsPMC Connector Pinouts P11 and P12 Pin Assignments Pin P13 Signal P14 Signal P13 and P14 Pin Assignments PMC Connector 6PMC Connector Outbound Doorbells System Controller Doorbell RegistersDoorbell Registers Inbound Doorbells System Controller 66 MHz Bus Operation Watchdog TimerReset MHZ BUS Operation Ethernet Interface MV64460 Ethernet Registers Ethernet Address Ethernet Interface Ethernet AddressEthernet Connection P1 Cable may result in a disconnection Pin SignalEthernet Interface Ethernet Connection P1 Mini-B USB Pin Description RJ45 Pin Blank Reset Command Register RCR Reset RegistersReset Event Register RER Cpld Cpld Reset Registers SCL Cpld Interrupt Registers Interrupt Registers Interrupt Enable Register IER Interrupt Pending Register IPR Eready Register Erdy Cpld Product ID Register PIRProduct ID Register PIR Revision Registers Hardware Version Register HVR Cpld Board Configuration RegistersBoard Configuration Registers PLD Version Register PVR Reserved Boot Blank MULTI-PROTOCOL Serial Controllers Mpsc BRGx Configuration RegisterSerial Input/Output Serial DMA Sdma Channels I2C Interface BRGx Tuning RegisterSerial Input/Output I2C Interface Connection Serial Input/Output I/O Connection Mini-USB Pin Description DB9 Pin Blank Real-Time Clock Block DiagramOperation Clock Operation Real-Time Clock Clock OperationAddress Data Function/Range Don’t care bit Blank Development Mezzanine Card DMC Circuit Board Development Mezzanine Card DMC Circuit Board Serial Numbers Connectors Development Mezzanine Card ConnectorsP1 Connector Pin Assignments OUT Dmcoe 3DMC P2 Mini-USB Connector P2 EIA-232 Interface PMPPC7448 to DMC Jtag Development Mezzanine Card PmPPC7448 to DMC JtagP3 JTAG/COP P4 Jtag Chain Header 6DMC P4 Jtag Chain Header Development Mezzanine Card DMC Jumpers JP1 DMC Jumpers JP1 Development Mezzanine Card Debug/Status LEDs Jumper Setting RegisterDEBUG/STATUS Leds DMC Setup Development Mezzanine Card DMC SetupInstalling the DMC Card DMC Location on PmPPC7448 Development Mezzanine Card Troubleshooting 10-14 COMMAND-LINE Features Monitor Monitor Basic Operation Power-up/Reset SequenceBasic Operation 2Power-up/Reset Sequence Flowchart Monitor Recovery and Updates Monitor Monitor Recovery and UpdatesPost Diagnostic Results Recovering the Monitor Updating the Monitor via Tftp Restoring the PmPPC7448 Monitor Using the KatanaQP PCI1 Resetting Environment Variables Verify that the checksum is correct Accessing the Console Over Ethernet Monitor Accessing the Console Over EthernetMonitor Command Reference Monitor Boot Commands Boot Commands Bootp BootelfBootm Bootv Monitor Memory Commands Memory Commands Find Definition mm .b, .w, .l address Erase Monitor Flash CommandsFlash Commands Flinfo Protect Monitor EEPROM/I2C CommandsEEPROM/I2C Commands Eeprom Imd Icrc32Iloop Imm Environment Parameter Commands Monitor Environment Parameter CommandsTest Commands Monitor Other Commands Other Commands Echo Crc32Date Enumpci Isdram HelpIminfo Loop Ping PciRun Monitor Environment Variables Environment Variables Bootfile Variable Description Binary Monitor TroubleshootingDownload Formats Motorola S-Record 11-26 GbE AcronymsCPSB PrPMC RMA Contents, table Cpld registers -1 to Index Index 11-17 UL certifications Blank 10006757-02 E R S O N. C O N S I D E R I T S O L V E D