



Central Processing Unit:
Processor Initialization 










XAE: Extended Addressing Enabled
0Disabled; the 4 MSB bits of the
1Enabled; the
NHR: Not Hard Reset (software use only)
0A hard reset occurred if software had previously set this bit
1A hard reset has not occurred
ICE/DCE: Instruction and Data Cache Enable
0Instruction and data caches are neither accessed nor updated
1Instruction and data caches are enabled
I/DLOCK: Instruction and Data Cache Lock bits
0Normal operation
1All the ways of the instruction and data caches are locked
ICFI/DCFI: Instruction and Data Cache Flash Invalidate bits
0Instruction and data caches are not invalidated
1An invalidate operation is issued that marks the state of each instruction and data cache block as invalid
SPD: Speculative DCache and ICache Access Disable
0Bus accesses to nonguarded space from both caches enabled
0Bus accesses to nonguarded space from both caches disabled
XBSEN: Extended BAT Block Size Enable
0Disables and clears to zero IBAT[XBL] and DBAT[XBL] bits
1Enables IBAT[XBL] and DBAT[XBL] bits
SGE: Store Gathering Enable
0Disabled
1Enabled
BTIC: Branch Target Instruction Cache Enable
0BTIC contents are invalidated and acts as if empty
1BTIC enables and new entries can be added
LRSTK: Link Register Stack Enable
0Link register prediction disabled
1Allows bclr and bclrl instructions to predict the branch target address using the link reg- ister stack
FOLD: Branch Folding Enable
0Disabled
1Enabled
PmPPC7448 User’s Manual |