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Emerson Development Mezzanine Card:PmPPC7448 to DMC JTAG, PMPPC7448 TO DMC JTAG, P3 JTAG/COP

Models: PMPPC7448

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Page 95

Image 95

Development Mezzanine Card:PmPPC7448 to DMC JTAG

PMPPC7448 TO DMC JTAG

Figure 10-4:PmPPC7448 to DMC JTAG Block Diagram

TDO

MPC7448_TDO

TDI

MPC7448_TDI

MPC7448

MPC7448_TCK

TCK

MPC7448_TMS

TMS

DEBUG_SRESET*

CKSTP_OUT*

TRST*

1.8 V

3.3V

DEBUG_HRESET*

HRESET*

SRESET*

MPC7448_CKSTP_OUT*

Convert

DEBUG_TRST*

MPC7448HRESET*

DEBUGHRESET B*

MPC7448 TRST*

MPC7448SRESET*

DEBUGSRESET B*

DEBUG TRST B*

TDO

CPLD_TDO

TCK

CPLD_TCK

MPC7448_SRESET_OUT*

CPLD

TMS

CPLD_TMS

Convert

MPC7448_HRESET_OUT*

Device

3.3 V

1.8V

CPLD

TDI

CPLD_TDI

MPC7448_TRST_OUT*

DMC Connector

Development

Mezzanine Card

(DMC)

COP Debug TDO 2 TDI TRST*

TCK

TMS

PLD JTAG

TCK 2 TDO

TMS

TDI 10

P3 JTAG/COP

The JTAG/COP interface provides for boundary-scan testing of the CPU and the PmPPC7448. This interface is compliant with the IEEE 1149.1 standard.

Figure 10-5:DMC P3 JTAG/COP Header

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10006757-02

PmPPC7448 User’s Manual

10-7

Page 95

Image 95

Emerson Development Mezzanine Card:PmPPC7448 to DMC JTAG, PMPPC7448 TO DMC JTAG, P3 JTAG/COP, MPC7448_TDI, Debug_Trst

Contents

User’s Manual PmPPC7448: PowerPC-BasedProcessor PMC ModuleDate Revision LevelPrincipal Changes EMC COMPLIANCE Regulatory Agency Warnings & NoticesFCC RULES AND REGULATIONS — PART Model Name/Number Regulatory Agency Warnings & NoticescontinuedManufacturer’s Name Product1 Overview Contents2 Setup 4On-CardMemory Configuration10Development Mezzanine Card Contentscontinued8 Serial Input/Output 9 Real-TimeClockContentscontinued 12 Acronyms10006757-02 blank pagePmPPC7448 User’s Manual Figures 10006757-02 blank pageviii PmPPC7448 User’s ManualTables 10006757-02 blank pagePmPPC7448 User’s Manual Registers 10006757-02 blank pagePmPPC7448 User’s Manual System Controller/PCI Bridge COMPONENTS AND FEATURESOverview SectionDevelopment Mezzanine Card DMC Overview: Components and FeaturesDevelopment Mezzanine Card DMC Overview: Functional OverviewFUNCTIONAL OVERVIEW Front PanelMemory Overview: Physical Memory MapPHYSICAL MEMORY MAP Hex AddressMode AccessHex Physical AddressProduct Certification SpecificationOverview: Additional Information ADDITIONAL INFORMATIONType UL CertificationSpecification Overview: Additional InformationDevice / Interface RoHS ComplianceTerminology and Notation Technical ReferencesDevice / Interface continuedOverview: Additional Information Document:10006757-02 blank page1-10 PmPPC7448 User’s ManualWidth SetupELECTROSTATIC DISCHARGE PMPPC7448 CIRCUIT BOARDSetup: PmPPC7448 Circuit Board Setup: PmPPC7448 Circuit Board C279Setup: PmPPC7448 Circuit Board ConnectorsSetup: PmPPC7448 Circuit Board LEDsSerial Reset SW1Front Panel EthernetSetup: PmPPC7448 Circuit Board Resetthe switch PMPPC7448 SETUP Setup: PmPPC7448 Setuprisk of damage to the board Power RequirementsWatt Requirements/Configuration Environmental ConsiderationsPmPPC7448PmPPC7448 BottomsideBottomside Installing the ModuleSetup: PmPPC7448 Setup baseboard Setup: TroubleshootingTROUBLESHOOTING Setup: Troubleshooting Technical SupportProduct ID Product RepairSetup: Troubleshooting Serial NumberRMA #____________ Emerson Network Power, Embedded ComputingTest and Repair Services Department 8310 Excelsior Drive Madison, WISection MPC7448 Key FeaturesCentral Processing Unit CategoryRegister PROCESSOR RESETDefault After Initialization Hex PROCESSOR INITIALIZATIONHardware Implementation Dependent 0 Register Central Processing Unit:Processor InitializationCentral Processing Unit:Processor Initialization XAE: Extended Addressing EnabledHID1BCLK HRESETHardware Implementation Dependent 1 Register HID1ECLKHID1ECLK Central Processing Unit:Exception HandlingEXCEPTION HANDLING HRESETException Instruction Dispatch/ExecutionPost-InstructionExecution PriorityNotes: continued Central Processing Unit:Exception ProcessingEXCEPTION PROCESSING Machine State RegisterCentral Processing Unit:Exception Processing FP Exception ModeFP Exception Mode: continued Central Processing Unit:Cache MemoryCACHE MEMORY L1 Cache Central Processing Unit:Cache Memory L2 CacheCentral Processing Unit:Cache Memory L2HWF: L2 Hardware Flush 0Flush disabledUSER FLASH On-CardMemory ConfigurationBOOT MEMORY CONFIGURATION Default ConfigurationNVRAM ALLOCATION On-CardMemory Configuration:On-CardSDRAMON-CARDSDRAM Name On-CardMemory Configuration:NVRAM AllocationWindow Size Address Offset hex10006757-02 blank pagePmPPC7448 User’s Manual Section System ControllerMEMORY INTERFACE DDR SDRAM Controller System Controller: CPU InterfaceCPU INTERFACE CPU Interface RegistersDEVICE CONTROLLER INTERFACE System Controller: Device Controller InterfaceInternal SRAM INTERNAL IDMA CONTROLLER Timer/CounterSystem Controller: Internal IDMA Controller Device Control RegistersPCI Read/Write PCI Configuration SpaceSystem Controller: PCI Interface PCI Subsystem Device and Vendor ID AssignmentSDRAM Size System Controller: PCI InterfaceSDRAM Size Max SDRAM SizeAD31:00 System Controller: PCI Bus Control SignalsPCI BUS CONTROL SIGNALS PCI Interface RegistersINTA*, INTB*, INTC*, INTD C/BE7:4EREADY: READY GNT*: GRANTSTOP*: STOP RESET_OUT*: RESET OUTPUTPRESENT*: PRESENT SERRP12 Signal System Controller: PMC Connector PinoutsPMC CONNECTOR PINOUTS P11 SignalSystem Controller: PMC Connector Pinouts P13 SignalP14 Signal P13 and P14 Pin AssignmentsP14 Signal PMC ConnectorSystem Controller: PMC Connector Pinouts P13 SignalInbound Doorbells System Controller: DoorbellRegistersDOORBELL REGISTERS Outbound Doorbells66 MHZ BUS OPERATION WATCHDOG TIMERRESET System Controller: 66 MHz Bus OperationSection Ethernet InterfaceMV64460 ETHERNET REGISTERS 00 80 F9 xx yy zz Ethernet Interface: Ethernet AddressETHERNET ADDRESS ETHERNET CONNECTION P1Mini-BUSB Pin SignalEthernet Interface: Ethernet Connection P1 cable may result in a disconnection10006757-02 blank pagePmPPC7448 User’s Manual CPLD RESET REGISTERSReset Event Register RER Reset Command Register RCRCPLD:Reset Registers INTERRUPT REGISTERS CPLD:Interrupt RegistersCPLD:Interrupt Registers Interrupt Enable Register IERInterrupt Pending Register IPR REVISION REGISTERS CPLD:Product ID Register PIRPRODUCT ID REGISTER PIR EREADY REGISTER ERDYPLD Version Register PVR CPLD:Board Configuration RegistersBOARD CONFIGURATION REGISTERS Hardware Version Register HVR0 DMC is not installed CPLD:Board Configuration Registers10006757-02 blank pagePmPPC7448 User’s Manual MULTI-PROTOCOLSERIAL CONTROLLERS MPSC BRGx Configuration RegisterMPSCx Main Configuration Registers Serial Input/OutputI/O CONNECTION BRGx Tuning RegisterSerial Input/Output: I2C Interface I2C INTERFACEDB9 Pin Serial Input/Output: I/O ConnectionMini-USBPin Description:210006757-02 blank pagePmPPC7448 User’s Manual Section BLOCK DIAGRAMReal-TimeClock OPERATIONFunction/Range Real-TimeClock: Clock OperationCLOCK OPERATION DataST: Stop bit 1=Stops the oscillator Real-TimeClock: Clock Operation10006757-02 blank pagePmPPC7448 User’s Manual Width Development Mezzanine CardDMC CIRCUIT BOARD SectionSerial Numbers Development Mezzanine Card:DMC Circuit BoardSignal Development Mezzanine Card:ConnectorsCONNECTORS P1 Connector Pin Assignments3.3V: 3.3 V is the power supply to the DMC analog Development Mezzanine Card:ConnectorsSignal SignalLED4:1 MPC7448_TDO MPC7448_TDI DEBUG_TRST CPU_VIO MPC7448_TCK DMC_BOOT_SRC DMC_JP4:3,1MPC7448_TMS DEBUG_SRESET DEBUG_HRESET DMC_OE WE0 LA17:2 BADDR2:0 AD7:0 FILT_TX FILT_RXSignal P2 EIA-232InterfaceDevelopment Mezzanine Card:Connectors SignalMPC7448HRESET Development Mezzanine Card:PmPPC7448 to DMC JTAGPMPPC7448 TO DMC JTAG P3 JTAG/COPDevelopment Mezzanine Card:PmPPC7448 to DMC JTAG P4 JTAG Chain HeaderSignal SignalSignal Development Mezzanine Card:DMC Jumpers JP1DMC JUMPERS JP1 SignalDEBUG/STATUS LEDS Jumper Setting RegisterDevelopment Mezzanine Card:Debug/Status LEDs Installing the DMC Card Development Mezzanine Card:DMC SetupDMC SETUP RJ45 Development Mezzanine Card:DMC SetupFigure DMC Location on PmPPC7448Product Repair Development Mezzanine Card:TroubleshootingTROUBLESHOOTING Technical Support8310 Excelsior Drive Madison, WI Emerson Network PowerDevelopment Mezzanine Card:Troubleshooting Test and Repair Services DepartmentSection COMMAND-LINEFEATURESMonitor BASIC OPERATION Power-up/ResetSequenceMonitor: Basic Operation baudrate Monitor: Basic Operation10006757-02 11-3Recovering the Monitor Monitor: Monitor Recovery and UpdatesPOST Diagnostic Results MONITOR RECOVERY AND UPDATESMonitor: Monitor Recovery and Updates Updating the Monitor via TFTP4Enter showpci at the command prompt Monitor: Monitor Recovery and UpdatesMonitor: Monitor Recovery and Updates Resetting Environment VariablesMONITOR COMMAND REFERENCE Monitor: Accessing the Console Over EthernetACCESSING THE CONSOLE OVER ETHERNET BOOT COMMANDS Monitor: Boot CommandsCommand Syntax Command Helpbootv bootelfbootm bootpMEMORY COMMANDS Monitor: Memory Commandsrarpboot tftpbootMonitor: Memory Commands findMonitor: Memory Commands flinfo Monitor: Flash CommandsFLASH COMMANDS eraseeeprom Monitor: EEPROM/I2C CommandsEEPROM/I2C COMMANDS protectDEFINITION: iprobe icrc32iloop iprobeprintenv Monitor: Environment Parameter CommandsENVIRONMENT PARAMETER COMMANDS TEST COMMANDSmtest Monitor: Other CommandsOTHER COMMANDS diagsenumpci crc32date echoloop helpiminfo isdramDEFINITION: ping host resetDEFINITION: reset pingshowmac DefaultMonitor: Environment Variables scriptVariable Description: continuedDefault Monitor: Environment VariablesVariable Variable:1Default Monitor: Environment VariablesMotorola S-Record Monitor: TroubleshootingDOWNLOAD FORMATS Binary10006757-02 blank page11-26 PmPPC7448 User’s ManualcPSB AcronymsASCII CPLDUART SDRAMSO-DIMM SROMIndex Index continued UL certifications . . . . . . . . . . . . . . . watchdog timer . . . . . . . . . . . . . .Index continued terminology . . . . . . . . . . . . . . . . . .10006757-02 blank pagePmPPC7448 User’s Manual Notes E M E R S O N. C O N S I D E R I T S O L V E D