PMPPC7448 to DMC Jtag, P3 JTAG/COP | Emerson manual

Development Mezzanine Card:PmPPC7448 to DMC JTAG

PMPPC7448 TO DMC JTAG

Figure 10-4:PmPPC7448 to DMC JTAG Block Diagram

TDO

MPC7448_TDO

TDI

MPC7448_TDI

MPC7448

MPC7448_TCK

TCK

MPC7448_TMS

TMS

DEBUG_SRESET*

CKSTP_OUT*

TRST*

1.8 V

3.3V

DEBUG_HRESET*

HRESET*

SRESET*

MPC7448_CKSTP_OUT*

Convert

DEBUG_TRST*

MPC7448HRESET*

DEBUGHRESET B*

MPC7448 TRST*

MPC7448SRESET*

DEBUGSRESET B*

DEBUG TRST B*

TDO

CPLD_TDO

TCK

CPLD_TCK

MPC7448_SRESET_OUT*

CPLD

TMS

CPLD_TMS

Convert

MPC7448_HRESET_OUT*

Device

3.3 V

1.8V

CPLD

TDI

CPLD_TDI

MPC7448_TRST_OUT*

DMC Connector

Development

Mezzanine Card

(DMC)

COP Debug TDO 2 TDI TRST*

TCK

TMS

15

16

PLD JTAG

TCK 2 TDO

TMS

TDI 10

P3 JTAG/COP

The JTAG/COP interface provides for boundary-scan testing of the CPU and the PmPPC7448. This interface is compliant with the IEEE 1149.1 standard.

Figure 10-5:DMC P3 JTAG/COP Header

16

215 1

10006757-02

PmPPC7448 User’s Manual

10-7

Image 95

Emerson user manual Development Mezzanine Card PmPPC7448 to DMC Jtag, PMPPC7448 to DMC Jtag, P3 JTAG/COP

Contents

PmPPC7448 PowerPC-Based Processor PMC Module Revision Level Principal Changes Date EMC Compliance Regulatory Agency Warnings & NoticesFCC Rules and Regulations Part Model Name/Number Manufacturer’s NameProduct Contents Contents Acronyms Blank Figures Viii Tables Blank Registers Xii Overview Components and Features Development Mezzanine Card DMC Overview Components and Features Functional Overview Overview Functional Overview Physical Memory MAP Overview Physical Memory Map EBFF,FFFF Hex Physical Access Address Mode Description See Product Certification Type SpecificationOverview Additional Information Additional Information EMC UL Certification Device / Interface Document RoHS ComplianceTerminology and Notation Technical References Document Device / Interface Intel StrataFlash Embedded Memory P30 Datasheet Blank Width Depth Height top side Height bottom side SetupElectrostatic Discharge PMPPC7448 Circuit Board C325 Setup PmPPC7448 Circuit Board PLD P14 Connectors 3LED Locations, Bottom LEDs Front Panel Front Panel Switch Reset PMPPC7448 Setup Setup PmPPC7448 Setup Environment Range Relative Humidity Power RequirementsEnvironmental Considerations Risk of damage to the board PMC Installing the Module Baseboard Setup TroubleshootingTroubleshooting Technical Support 8Serial Number and Product ID on Bottom Side Product Repair Setup Troubleshooting Central Processing Unit Category MPC7448 Key Features Processor Initialization Processor ResetRegister Default After Initialization Hex Hardware Implementation Dependent 0 Register Central Processing Unit Processor Initialization Central Processing Unit Processor Initialization Hardware Implementation Dependent 1 Register Exception Handling Central Processing Unit Exception Handling Priority Exception Post-Instruction Execution Machine State Register Central Processing Unit Exception ProcessingException Processing FE0 FE1 FP Exception Mode L1 Cache Central Processing Unit Cache MemoryCache Memory L2 Cache Central Processing Unit Cache Memory User Flash On-Card Memory ConfigurationBoot Memory Configuration Jumper Function Options Default Configuration Nvram Allocation On-Card Memory Configuration On-Card SdramON-CARD Sdram Address Offset hex Name Bytes On-Card Memory Configuration Nvram AllocationWindow Size Blank XOR System Controller Memory Interface System Controller CPU InterfaceCPU Interface CPU Interface Registers Device Controller Interface System Controller Device Controller InterfaceInternal Sram Internal Idma Controller Timer/CounterSystem Controller Internal Idma Controller Device Control Registers PCI Read/Write PCI Configuration SpaceSystem Controller PCI Interface PCI Subsystem Device and Vendor ID Assignment Sdram Size PCI Interface Registers System Controller PCI Bus Control SignalsPCI BUS Control Signals Eready Ready PRESENT* Present P11 and P12 Pin Assignments System Controller PMC Connector PinoutsPMC Connector Pinouts Pin P11 Signal P12 Signal P13 and P14 Pin Assignments Pin P13 Signal P14 Signal 6PMC Connector PMC Connector Inbound Doorbells System Controller Doorbell RegistersDoorbell Registers Outbound Doorbells MHZ BUS Operation Watchdog TimerReset System Controller 66 MHz Bus Operation MV64460 Ethernet Registers Ethernet Interface Ethernet Connection P1 Ethernet Interface Ethernet AddressEthernet Address Mini-B USB Pin Description RJ45 Pin Pin SignalEthernet Interface Ethernet Connection P1 Cable may result in a disconnection Blank Cpld Reset RegistersReset Event Register RER Reset Command Register RCR SCL Cpld Reset Registers Interrupt Registers Cpld Interrupt Registers Interrupt Pending Register IPR Interrupt Enable Register IER Revision Registers Cpld Product ID Register PIRProduct ID Register PIR Eready Register Erdy PLD Version Register PVR Cpld Board Configuration RegistersBoard Configuration Registers Hardware Version Register HVR Reserved Boot Blank Serial DMA Sdma Channels BRGx Configuration RegisterSerial Input/Output MULTI-PROTOCOL Serial Controllers Mpsc Connection BRGx Tuning RegisterSerial Input/Output I2C Interface I2C Interface Mini-USB Pin Description DB9 Pin Serial Input/Output I/O Connection Blank Operation Block DiagramReal-Time Clock Address Data Function/Range Real-Time Clock Clock OperationClock Operation Don’t care bit Blank DMC Circuit Board Development Mezzanine Card Serial Numbers Development Mezzanine Card DMC Circuit Board P1 Connector Pin Assignments Development Mezzanine Card ConnectorsConnectors OUT Dmcoe P2 EIA-232 Interface 3DMC P2 Mini-USB Connector P3 JTAG/COP Development Mezzanine Card PmPPC7448 to DMC JtagPMPPC7448 to DMC Jtag 6DMC P4 Jtag Chain Header P4 Jtag Chain Header DMC Jumpers JP1 Development Mezzanine Card DMC Jumpers JP1 DEBUG/STATUS Leds Jumper Setting RegisterDevelopment Mezzanine Card Debug/Status LEDs Installing the DMC Card Development Mezzanine Card DMC SetupDMC Setup DMC Location on PmPPC7448 Development Mezzanine Card Troubleshooting 10-14 Monitor COMMAND-LINE Features Basic Operation Power-up/Reset SequenceMonitor Basic Operation 2Power-up/Reset Sequence Flowchart Recovering the Monitor Monitor Monitor Recovery and UpdatesPost Diagnostic Results Monitor Recovery and Updates Updating the Monitor via Tftp PCI1 Restoring the PmPPC7448 Monitor Using the KatanaQP Verify that the checksum is correct Resetting Environment Variables Monitor Command Reference Monitor Accessing the Console Over EthernetAccessing the Console Over Ethernet Boot Commands Monitor Boot Commands Bootv BootelfBootm Bootp Memory Commands Monitor Memory Commands Find Definition mm .b, .w, .l address Flinfo Monitor Flash CommandsFlash Commands Erase Eeprom Monitor EEPROM/I2C CommandsEEPROM/I2C Commands Protect Imm Icrc32Iloop Imd Test Commands Monitor Environment Parameter CommandsEnvironment Parameter Commands Other Commands Monitor Other Commands Enumpci Crc32Date Echo Loop HelpIminfo Isdram Run PciPing Environment Variables Monitor Environment Variables Bootfile Variable Description Motorola S-Record Monitor TroubleshootingDownload Formats Binary 11-26 PrPMC AcronymsCPSB GbE RMA Index Contents, table Cpld registers -1 to 11-17 Index UL certifications Blank 10006757-02 E R S O N. C O N S I D E R I T S O L V E D