Central Processing Unit Cache Memory, L1 Cache | Emerson PMPPC7448

Central Processing Unit:Cache Memory


FE0:							FE1:							FP Exception Mode: (continued)
1						0								Imprecise recoverable
1						1								Precise

SE: Single-Step Trace enable

0Executes instructions normally

1Single-step trace exception generated

BE: Branch Trace enable

0Executes instructions normally

1Branch type trace exception generated

IP: Exception Prefix

0Places the exception vector table at the base of RAM (0000,000016)

1Places the exception vector table at the base of ROM (FFF0,000016)

IR/DR: Instruction and Data address translation enables

0Address translation disabled

1Address translation enabled

PMM: Marks a process for the Performance Monitor

0Process is not marked

1Process is marked

RI: Recoverable exception enable for system reset and machine check—this feature is enabled on initial power-up.

0Exception is not recoverable

1Exception is recoverable

LE: Little-endian mode enable

0Big-endian mode (default)

1Little-endian mode

CACHE MEMORY

L1 Cache

The MPC7448 processor implements two separate 32-kilobyte, level-one (L1) instruction and data caches that are eight-way, set-associative. The L1 supports a four-state modi- fied/exclusive/shared/invalid (MESI) cache coherency protocol. The caches also employ pseudo least-recently-used (PLRU) replacement algorithms within each way.

3-10

PmPPC7448 User’s Manual

10006757-02

Image 48

Emerson PMPPC7448 user manual Central Processing Unit Cache Memory, L1 Cache

Contents

PmPPC7448 PowerPC-Based Processor PMC Module Revision Level Principal Changes Date Regulatory Agency Warnings & Notices FCC Rules and Regulations PartEMC Compliance Manufacturer’s Name ProductModel Name/Number Contents Contents Acronyms Blank Figures Viii Tables Blank Registers Xii Components and Features Overview Overview Components and Features Development Mezzanine Card DMC Overview Functional Overview Functional Overview Overview Physical Memory Map Physical Memory MAP Hex Physical Access Address Mode Description See EBFF,FFFF Type Specification Overview Additional InformationAdditional Information Product Certification UL Certification EMC RoHS Compliance Terminology and NotationTechnical References Device / Interface Document Intel StrataFlash Embedded Memory P30 Datasheet Document Device / Interface Blank Setup Electrostatic DischargePMPPC7448 Circuit Board Width Depth Height top side Height bottom side Setup PmPPC7448 Circuit Board C325 PLD Connectors P14 LEDs 3LED Locations, Bottom Front Panel Front Panel Reset Switch Setup PmPPC7448 Setup PMPPC7448 Setup Power Requirements Environmental ConsiderationsRisk of damage to the board Environment Range Relative Humidity Installing the Module PMC Setup Troubleshooting TroubleshootingBaseboard Technical Support Product Repair 8Serial Number and Product ID on Bottom Side Setup Troubleshooting Category MPC7448 Key Features Central Processing Unit Processor Reset Register Default After Initialization HexProcessor Initialization Central Processing Unit Processor Initialization Hardware Implementation Dependent 0 Register Central Processing Unit Processor Initialization Hardware Implementation Dependent 1 Register Central Processing Unit Exception Handling Exception Handling Post-Instruction Execution Priority Exception Central Processing Unit Exception Processing Exception ProcessingMachine State Register FE0 FE1 FP Exception Mode Central Processing Unit Cache Memory Cache MemoryL1 Cache L2 Cache Central Processing Unit Cache Memory On-Card Memory Configuration Boot Memory ConfigurationJumper Function Options Default Configuration User Flash On-Card Memory Configuration On-Card Sdram ON-CARD SdramNvram Allocation On-Card Memory Configuration Nvram Allocation Window SizeAddress Offset hex Name Bytes Blank System Controller XOR System Controller CPU Interface CPU InterfaceCPU Interface Registers Memory Interface System Controller Device Controller Interface Internal SramDevice Controller Interface Timer/Counter System Controller Internal Idma ControllerDevice Control Registers Internal Idma Controller PCI Configuration Space System Controller PCI InterfacePCI Subsystem Device and Vendor ID Assignment PCI Read/Write Sdram Size System Controller PCI Bus Control Signals PCI BUS Control SignalsPCI Interface Registers Eready Ready PRESENT* Present System Controller PMC Connector Pinouts PMC Connector PinoutsPin P11 Signal P12 Signal P11 and P12 Pin Assignments Pin P13 Signal P14 Signal P13 and P14 Pin Assignments PMC Connector 6PMC Connector System Controller Doorbell Registers Doorbell RegistersOutbound Doorbells Inbound Doorbells Watchdog Timer ResetSystem Controller 66 MHz Bus Operation MHZ BUS Operation Ethernet Interface MV64460 Ethernet Registers Ethernet Interface Ethernet Address Ethernet AddressEthernet Connection P1 Pin Signal Ethernet Interface Ethernet Connection P1Cable may result in a disconnection Mini-B USB Pin Description RJ45 Pin Blank Reset Registers Reset Event Register RERReset Command Register RCR Cpld Cpld Reset Registers SCL Cpld Interrupt Registers Interrupt Registers Interrupt Enable Register IER Interrupt Pending Register IPR Cpld Product ID Register PIR Product ID Register PIREready Register Erdy Revision Registers Cpld Board Configuration Registers Board Configuration RegistersHardware Version Register HVR PLD Version Register PVR Reserved Boot Blank BRGx Configuration Register Serial Input/OutputMULTI-PROTOCOL Serial Controllers Mpsc Serial DMA Sdma Channels BRGx Tuning Register Serial Input/Output I2C InterfaceI2C Interface Connection Serial Input/Output I/O Connection Mini-USB Pin Description DB9 Pin Blank Block Diagram Real-Time ClockOperation Real-Time Clock Clock Operation Clock OperationAddress Data Function/Range Don’t care bit Blank Development Mezzanine Card DMC Circuit Board Development Mezzanine Card DMC Circuit Board Serial Numbers Development Mezzanine Card Connectors ConnectorsP1 Connector Pin Assignments OUT Dmcoe 3DMC P2 Mini-USB Connector P2 EIA-232 Interface Development Mezzanine Card PmPPC7448 to DMC Jtag PMPPC7448 to DMC JtagP3 JTAG/COP P4 Jtag Chain Header 6DMC P4 Jtag Chain Header Development Mezzanine Card DMC Jumpers JP1 DMC Jumpers JP1 Jumper Setting Register Development Mezzanine Card Debug/Status LEDsDEBUG/STATUS Leds Development Mezzanine Card DMC Setup DMC SetupInstalling the DMC Card DMC Location on PmPPC7448 Development Mezzanine Card Troubleshooting 10-14 COMMAND-LINE Features Monitor Power-up/Reset Sequence Monitor Basic OperationBasic Operation 2Power-up/Reset Sequence Flowchart Monitor Monitor Recovery and Updates Post Diagnostic ResultsMonitor Recovery and Updates Recovering the Monitor Updating the Monitor via Tftp Restoring the PmPPC7448 Monitor Using the KatanaQP PCI1 Resetting Environment Variables Verify that the checksum is correct Monitor Accessing the Console Over Ethernet Accessing the Console Over EthernetMonitor Command Reference Monitor Boot Commands Boot Commands Bootelf BootmBootp Bootv Monitor Memory Commands Memory Commands Find Definition mm .b, .w, .l address Monitor Flash Commands Flash CommandsErase Flinfo Monitor EEPROM/I2C Commands EEPROM/I2C CommandsProtect Eeprom Icrc32 IloopImd Imm Monitor Environment Parameter Commands Environment Parameter CommandsTest Commands Monitor Other Commands Other Commands Crc32 DateEcho Enumpci Help IminfoIsdram Loop Pci PingRun Monitor Environment Variables Environment Variables Bootfile Variable Description Monitor Troubleshooting Download FormatsBinary Motorola S-Record 11-26 Acronyms CPSBGbE PrPMC RMA Contents, table Cpld registers -1 to Index Index 11-17 UL certifications Blank 10006757-02 E R S O N. C O N S I D E R I T S O L V E D