Emerson PMPPC7448 user manual Central Processing Unit:Cache Memory, CACHE MEMORY L1 Cache

Central Processing Unit:Cache Memory

FE0:		FE1:	FP Exception Mode: (continued)
1	0		Imprecise recoverable
1	1		Precise

SE: Single-Step Trace enable

0Executes instructions normally

1Single-step trace exception generated

BE: Branch Trace enable

0Executes instructions normally

1Branch type trace exception generated

IP: Exception Prefix

0Places the exception vector table at the base of RAM (0000,000016)

1Places the exception vector table at the base of ROM (FFF0,000016)

IR/DR: Instruction and Data address translation enables

0Address translation disabled

1Address translation enabled

PMM: Marks a process for the Performance Monitor

0Process is not marked

1Process is marked

RI: Recoverable exception enable for system reset and machine check—this feature is enabled on initial power-up.

0Exception is not recoverable

1Exception is recoverable

LE: Little-endian mode enable

0Big-endian mode (default)

1Little-endian mode

CACHE MEMORY

L1 Cache

The MPC7448 processor implements two separate 32-kilobyte, level-one (L1) instruction and data caches that are eight-way, set-associative. The L1 supports a four-state modi- fied/exclusive/shared/invalid (MESI) cache coherency protocol. The caches also employ pseudo least-recently-used (PLRU) replacement algorithms within each way.

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PmPPC7448 User’s Manual 10006757-02