Central Processing Unit Exception Processing | Emerson PMPPC7448

Central Processing Unit:Exception Processing

Priority:

Exception:

Notes: (continued)

9

Data Storage (DSI)

Due to eciwx, ecowx with EAR(E)=0

(DSISR[11])

10

Data Storage (DSI)

Due to lwarx/stwcx

11

Data Storage (DSI)

Due to BAT/page protection violation

(DSISR[4]) or lwarx/stwcx to BAT entry

12

Data Storage (DSI)

Due to any access except cache operations to

SR[T]=1 (DSISR[5]) or T=0->T=1 crossing

13

Data TLB miss on store

Due to store miss in DTLB with HID0[STEN]=1

14

Data TLB miss-on-load

Due to load miss in DTLB with HID0[STEN]=1

15

Data Storage (DSI)

Due to TLB detects page protection violation

(DSISR[4]), lwarx/stwcx to page table entry, or

hardware table search page fault (DSISR[1])

16

Data TLB miss on store

Due to HID0[STEN]=1 and the PTE changed bit

not set (C=0) for a store operation

17

Data Storage (DSI)

Due to DABR address match (DSISR[9])

18

AltiVec Assist

Denormalized data detected as input or output

in the AltiVec vector floating-point unit (VFPU)

while in Java mode (VSCR[NJ]=0)

Post-Instruction Execution Exceptions

19

Trace

Lowest priority—due to MSR[SE]=1

(or MSR[BE]=1 for branches)

EXCEPTION PROCESSING

When an exception occurs, the address saved in Machine Status Save/Restore register 0 (SRR0) helps determine where instruction processing should resume when the exception handler returns control to the interrupted process. Machine Status Save/Restore register 1 (SRR1) is used to save machine status on exceptions and to restore those values when an rfi instruction is executed.

When an exception is taken, the MPC7448 controller uses SRR0 and SRR1 to save the con- tents of the Machine State register (MSR) for the current context and to identify where instruction execution resumes after the exception is handled.

Machine State Register

The Machine State register (MSR) configures the state of the MPC7448 CPU. On initial power-up of the PmPPC7448, most of the MSR bits are cleared. Please refer to the MPC7450 RISC Microprocessor Family User’s Manual for more detailed descriptions of the individual bit fields.

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PmPPC7448 User’s Manual

10006757-02

Image 46

Emerson PMPPC7448 user manual Central Processing Unit Exception Processing, Machine State Register

Contents

PmPPC7448 PowerPC-Based Processor PMC Module Revision Level Principal Changes Date FCC Rules and Regulations Part Regulatory Agency Warnings & NoticesEMC Compliance Product Manufacturer’s NameModel Name/Number Contents Contents Acronyms Blank Figures Viii Tables Blank Registers Xii Components and Features Overview Overview Components and Features Development Mezzanine Card DMC Overview Functional Overview Functional Overview Overview Physical Memory Map Physical Memory MAP Hex Physical Access Address Mode Description See EBFF,FFFF Additional Information Type SpecificationOverview Additional Information Product Certification UL Certification EMC Technical References RoHS ComplianceTerminology and Notation Device / Interface Document Intel StrataFlash Embedded Memory P30 Datasheet Document Device / Interface Blank PMPPC7448 Circuit Board SetupElectrostatic Discharge Width Depth Height top side Height bottom side Setup PmPPC7448 Circuit Board C325 PLD Connectors P14 LEDs 3LED Locations, Bottom Front Panel Front Panel Reset Switch Setup PmPPC7448 Setup PMPPC7448 Setup Risk of damage to the board Power RequirementsEnvironmental Considerations Environment Range Relative Humidity Installing the Module PMC Troubleshooting Setup TroubleshootingBaseboard Technical Support Product Repair 8Serial Number and Product ID on Bottom Side Setup Troubleshooting Category MPC7448 Key Features Central Processing Unit Register Default After Initialization Hex Processor ResetProcessor Initialization Central Processing Unit Processor Initialization Hardware Implementation Dependent 0 Register Central Processing Unit Processor Initialization Hardware Implementation Dependent 1 Register Central Processing Unit Exception Handling Exception Handling Post-Instruction Execution Priority Exception Exception Processing Central Processing Unit Exception ProcessingMachine State Register FE0 FE1 FP Exception Mode Cache Memory Central Processing Unit Cache MemoryL1 Cache L2 Cache Central Processing Unit Cache Memory Jumper Function Options Default Configuration On-Card Memory ConfigurationBoot Memory Configuration User Flash ON-CARD Sdram On-Card Memory Configuration On-Card SdramNvram Allocation Window Size On-Card Memory Configuration Nvram AllocationAddress Offset hex Name Bytes Blank System Controller XOR CPU Interface Registers System Controller CPU InterfaceCPU Interface Memory Interface Internal Sram System Controller Device Controller InterfaceDevice Controller Interface Device Control Registers Timer/CounterSystem Controller Internal Idma Controller Internal Idma Controller PCI Subsystem Device and Vendor ID Assignment PCI Configuration SpaceSystem Controller PCI Interface PCI Read/Write Sdram Size PCI BUS Control Signals System Controller PCI Bus Control SignalsPCI Interface Registers Eready Ready PRESENT* Present Pin P11 Signal P12 Signal System Controller PMC Connector PinoutsPMC Connector Pinouts P11 and P12 Pin Assignments Pin P13 Signal P14 Signal P13 and P14 Pin Assignments PMC Connector 6PMC Connector Outbound Doorbells System Controller Doorbell RegistersDoorbell Registers Inbound Doorbells System Controller 66 MHz Bus Operation Watchdog TimerReset MHZ BUS Operation Ethernet Interface MV64460 Ethernet Registers Ethernet Address Ethernet Interface Ethernet AddressEthernet Connection P1 Cable may result in a disconnection Pin SignalEthernet Interface Ethernet Connection P1 Mini-B USB Pin Description RJ45 Pin Blank Reset Command Register RCR Reset RegistersReset Event Register RER Cpld Cpld Reset Registers SCL Cpld Interrupt Registers Interrupt Registers Interrupt Enable Register IER Interrupt Pending Register IPR Eready Register Erdy Cpld Product ID Register PIRProduct ID Register PIR Revision Registers Hardware Version Register HVR Cpld Board Configuration RegistersBoard Configuration Registers PLD Version Register PVR Reserved Boot Blank MULTI-PROTOCOL Serial Controllers Mpsc BRGx Configuration RegisterSerial Input/Output Serial DMA Sdma Channels I2C Interface BRGx Tuning RegisterSerial Input/Output I2C Interface Connection Serial Input/Output I/O Connection Mini-USB Pin Description DB9 Pin Blank Real-Time Clock Block DiagramOperation Clock Operation Real-Time Clock Clock OperationAddress Data Function/Range Don’t care bit Blank Development Mezzanine Card DMC Circuit Board Development Mezzanine Card DMC Circuit Board Serial Numbers Connectors Development Mezzanine Card ConnectorsP1 Connector Pin Assignments OUT Dmcoe 3DMC P2 Mini-USB Connector P2 EIA-232 Interface PMPPC7448 to DMC Jtag Development Mezzanine Card PmPPC7448 to DMC JtagP3 JTAG/COP P4 Jtag Chain Header 6DMC P4 Jtag Chain Header Development Mezzanine Card DMC Jumpers JP1 DMC Jumpers JP1 Development Mezzanine Card Debug/Status LEDs Jumper Setting RegisterDEBUG/STATUS Leds DMC Setup Development Mezzanine Card DMC SetupInstalling the DMC Card DMC Location on PmPPC7448 Development Mezzanine Card Troubleshooting 10-14 COMMAND-LINE Features Monitor Monitor Basic Operation Power-up/Reset SequenceBasic Operation 2Power-up/Reset Sequence Flowchart Monitor Recovery and Updates Monitor Monitor Recovery and UpdatesPost Diagnostic Results Recovering the Monitor Updating the Monitor via Tftp Restoring the PmPPC7448 Monitor Using the KatanaQP PCI1 Resetting Environment Variables Verify that the checksum is correct Accessing the Console Over Ethernet Monitor Accessing the Console Over EthernetMonitor Command Reference Monitor Boot Commands Boot Commands Bootp BootelfBootm Bootv Monitor Memory Commands Memory Commands Find Definition mm .b, .w, .l address Erase Monitor Flash CommandsFlash Commands Flinfo Protect Monitor EEPROM/I2C CommandsEEPROM/I2C Commands Eeprom Imd Icrc32Iloop Imm Environment Parameter Commands Monitor Environment Parameter CommandsTest Commands Monitor Other Commands Other Commands Echo Crc32Date Enumpci Isdram HelpIminfo Loop Ping PciRun Monitor Environment Variables Environment Variables Bootfile Variable Description Binary Monitor TroubleshootingDownload Formats Motorola S-Record 11-26 GbE AcronymsCPSB PrPMC RMA Contents, table Cpld registers -1 to Index Index 11-17 UL certifications Blank 10006757-02 E R S O N. C O N S I D E R I T S O L V E D