Development Mezzanine Card:PmPPC7448 to DMC JTAG
Table
Pin: | Signal: | Pin: | Signal: |
1 | MPC7448_TDO | 2 | Not connected |
3 | MPC7448_TDI | 4 | DEBUG_TRST* |
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5 | Not connected | 6 | JTAG_PWR (1.8 V) |
7 | MPC7448_TCK | 8 | Not connected |
9 | MPC7448_TMS | 10 | Not connected |
11 | DEBUG_SRESET* | 12 | GND |
13 | DEBUG_HRESET* | 14 | Key22 |
15 | MPC7448CKSTP_OUT* | 16 | GND |
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|
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2. Pin 14 is not installed.
MPC7448 CKSTP_OUT*:Checkstop
DEBUG_HRESET*: Hard
DEBUG_SRESET*: Soft
MPC7448_TCK: Test Clock
MPC7448_TDI: Test Data
MPC7448_TDO: Test Data
MPC7448_TMS: Test Mode
DEBUG_TRST*: Test
P4 JTAG Chain Header
This header allows access to the CPLD programming interface.
Figure 10-6: DMC P4 JTAG Chain Header
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PmPPC7448 User’s Manual |